Code generator circuit

A code generator circuit for dividing input data input to a bit serial by a predetermined generator polynomial to generate a division remainder, comprising:

• division means configured as a shift register where a plurality of flip-flops, selector circuits respectively added immediately before said flip flops, and exclusive-OR circuits inserted according to said generator polynomial are serially connected, and
• a remainder shift circuit for comparing the number of digits of leading 0s of the value on said shift register with the number of leading 0s of the subsequent input data, assuming the number of digits of the smaller as the number of skip digits, then outputting said value on the shift register shifted by said number of skip digits,
• wherein said selector circuits select the output of said remainder shift circuit when said number of skip digits is 1 or more and select the output of the flip-flops connected immediately before the respective selector circuits when said number of skip digits is 0.