Error control coding method and system for non-volatile memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYue Der Chih
Life of this patent
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Abstract
Methods and systems for improving repairing efficiency in non-volatile memory. Repairing data may be read from an information array associated with the non-volatile memory. The repairing data is generally read to a volatile latch associated with the non-volatile memory. An error correction coding circuit (ECC) circuit can be enabled during reading of the repairing data to thereby identify and repair defective columns or rows associated with the non-volatile memory, regardless of the corruption of the columns.
Claims20
A method for improving repairing efficiency in a non-volatile memory, said method comprising the steps of:
- reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory;
- and
- enabling an error correction coding circuit during reading of said repairing data to thereby identify and repair defective columns or rows associated with said non-volatile memory regardless of the corruption of said columns or rows.
A method for improving repairing efficiency in a non-volatile memory, said method comprising the steps of:
- reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory;
- and
- enabling an error correction coding circuit during an access of a main array associated with said non-volatile memory to thereby correct correctable errors if a particular address corresponds to an address of at least one defective column or row, wherein said particular address comprises a Y-address corresponding to said at least one defective column or row.
A method for improving repairing efficiency in a non-volatile memory, said method comprising the steps of:
- reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory, wherein said column repair data is read utilizing a read circuit linked to a main array associated with said non-volatile memory and an error correction coding circuit linked to said volatile latch and a decoder circuit;
- and
- enabling said error correction coding circuit during an access of said main array to thereby correct correctable errors if a particular address corresponds to an address of at least one defective column or row, wherein said particular address comprises a Y-address corresponding to said at least one defective column or row.
A method for improving repairing efficiency in a non-volatile memory, said method comprising the steps of:
- reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory, wherein said column repair data is read utilizing a read circuit linked to a main array associated with said non-volatile memory and an error correction coding circuit linked to said volatile latch and a decoder circuit;
- and
- enabling said error correction coding circuit during reading of said repairing data to thereby identify and repair defective columns or rows associated with said non-volatile memory regardless of the corruption of said columns or rows.
A method for improving repairing efficiency in a non-volatile memory, said method comprising the steps of:
- reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory following initialization of a computer system associated with said non-volatile memory, wherein said column repair data is read utilizing a read circuit linked to a main array associated with said non-volatile memory and an error correction coding circuit linked to said volatile latch and a decoder circuit;
- and
- enabling said error correction coding circuit during reading of said repairing data to thereby identify and repair defective columns or rows associated with said non-volatile memory regardless of the corruption of said columns or rows.
A system for improving repairing efficiency in a non-volatile memory, said system comprising:
- reading circuit for reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory;
- and
- an error correction coding circuit enabled during reading of said repairing data to thereby identify and repair defective columns or rows associated with said non-volatile memory regardless of the corruption of said columns or rows.
A system for improving repairing efficiency in a non-volatile memory, said system comprising:
- read circuit for reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory;
- and
- an error correction coding circuit enabled during an access of a main array associated with said non-volatile memory to thereby correct correctable errors if a particular address corresponds to an address of at least one defective column, wherein said particular address comprises a Y-address corresponding to said at least one defective column or row.
A system for improving repairing efficiency in a non-volatile memory, said system comprising:
- read circuit for reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory, wherein said column repair data is read utilizing a read circuit linked to a main array associated with said non-volatile memory and an error correction coding circuit linked to said volatile latch and a decoder circuit;
- and
- said error correction coding circuit enabled during an access of said main array to thereby correct correctable errors if a particular address corresponds to an address of at least one defective column, wherein said particular address comprises a Y-address corresponding to said at least one defective column or row.
A system for improving repairing efficiency in a non-volatile memory, said system comprising:
- a read circuit for reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory, wherein said column repair data is read utilizing a read circuit linked to a main array associated with said non-volatile memory and an error correction coding circuit linked to said volatile latch and a decoder circuit;
- and
- said error correction coding circuit enabled during reading of said repairing data to thereby identify and repair defective columns or rows associated with said non-volatile memory regardless of the corruption of said columns or rows.
A system for improving repairing efficiency in a non-volatile memory, said system comprising:
- a read circuit for reading repairing data from an information array associated with said non-volatile memory to a volatile latch associated with said non-volatile memory following initialization of a computer system associated with said non-volatile memory, wherein said column repair data is read utilizing a read circuit linked to a main array associated with said non-volatile memory and an error correction coding circuit linked to said volatile latch and a decoder circuit;
- and
- said error correction coding circuit enabled during reading of said repairing data to thereby identify and repair defective columns or rows associated with said non-volatile memory regardless of the corruption of said columns or rows.
Dependencies are inferred from the claim text.