Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

A system that accepts virtual scan patterns stored in an ATE (automatic test equipment) for generating broadcast scan patterns to test a scan-based integrated circuit, a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said system comprising:

• a) placing said broadcaster between said ATE and said scan-based integrated circuit;
• b) transmitting a new said virtual scan pattern stored in said ATE to said broadcaster for generating said broadcast scan pattern to test manufacturing faults in said scan-based integrated circuit;
• c) comparing the test response of said scan-based integrated circuit with the expected test response;
• and
• d) repeating steps (b) to (c) until predetermined limiting criteria are met.

A system that accepts virtual scan patterns stored in an ATE (automatic test equipment) for generating broadcast scan patterns to test a scan-based integrated circuit, a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said system comprising:

• a) using simulation, modeling said broadcaster in said ATE;
• b) applying a new said virtual scan pattern stored in said ATE to generate said broadcast scan pattern using the simulated broadcaster model;
• c) transmitting said broadcast scan pattern generated by said broadcaster in said ATE to said scan chains in said scan-based integrated circuit for testing manufacturing faults in said scan-based integrated circuit;
• d) comparing the test response of said scan-based integrated circuit with the expected test response;
• and
• e) repeating steps (b) to (d) until predetermined limiting criteria are met.

A method that reorders scan cells for generating broadcast scan patterns to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to a broadcaster, said method comprising the steps of:

• a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;
• b) establishing an original scan order and a set of scan order constraints on selected scan chains based on the design of said broadcaster;
• c) transforming said sequential circuit model into an equivalent combinational circuit model;
• d) performing an input-cone analysis on selected scan cells in said selected scan chains according to said original scan order and said scan order constraints;
• and
• e) generating an optimal scan order to minimize the inter-dependency of said selected scan cells on said selected scan chains to be positioned on the same shift cycle.

A method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said method comprising the steps of:

• a) compiling the HDL (hardware description language) code modeled at gate-level that represents said scan-based integrated circuit into a sequential circuit model;
• b) establishing a set of input constraints on selected scan cells based on the predetermined values to be assigned on said broadcaster during each shift cycle or between test sessions;
• c) transforming said sequential circuit model into an equivalent combinational circuit model;
• d) generating said broadcast scan patterns according to said set of input constraints;
• and
• e) re-assigning a new set of input constraints and repeating step (d) until a predetermined limiting criteria are met.

A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said method comprising the steps of:

• a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;
• b) establishing a set of input constraints on selected scan cells based on the predetermined values to be assigned on said broadcaster during each shift cycle or between test sessions;
• c) transforming said sequential circuit model into an equivalent combinational circuit model;
• d) generating said broadcast scan patterns according to said set of input constraints;
• and
• e) re-assigning a new set of input constraints and repeating step (d) until predetermined limiting criteria are met.

An electronic design automation system comprising:

• a processor;
• a bus coupled to said processor;
• and
• a computer-readable memory coupled to said bus and having computer-readable program code stored therein for causing said electronic design automation system to perform a method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the broadcaster, said method comprising the steps of:
• a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;
• b) establishing a set of input constraints on selected scan cells based on the predetermined values to be assigned on said broadcaster during each shift cycle or between test sessions;
• c) transforming said sequential circuit model into an equivalent combinational circuit model;
• d) generating said broadcast scan patterns according to said set of input constraints;
• and
• e) re-assigning a new set of input constraints and repeating step (d) until predetermined limiting criteria are met.

A method that synthesizes a broadcaster and a compactor to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs coupled to the broadcaster and the scan chain outputs coupled to the compactor, said method comprising the steps of:

• a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;
• b) establishing constraints on said broadcaster, said compactor, and for stitching;
• c) synthesizing said broadcaster according to said constraints specified on said broadcaster;
• d) synthesizing said compactor according to said constraints specified on said compactor;
• e) stitching said broadcaster and said compactor on said sequential circuit model according to said constraints specified for stitching;
• and
• f) generating synthesized HDL code modeled at RTL or gate-level.