Method for identifying test points to optimize the testing of integrated circuits using a genetic algorithm
AssigneeInternational Business Machines Corporation
InventorsDavid G. Scott, Faisal R. Khoja
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AssigneeInternational Business Machines Corporation
InventorsDavid G. Scott, Faisal R. Khoja
Estimating the term…
A method for identifying, by way of a genetic algorithm, test points to be inserted in an integrated circuit (IC) chip to improve the testability of the IC is described. The algorithm is particularly well suited for large circuit designs (several million gates) because it allows to simultaneous insert multiple additional test points at critical locations of the IC to gain supplemental controlability and/or observability and thereby eliminating the drawbacks associated with the single test point approach. To further improve performance, cost function gradient techniques are applied to guide the selection of potential test points for consideration by the algorithm. Fault simulation of random patterns is used to more accurately distinguish between random pattern testable and random resistant faults, and to provide a more accurate set of initial probabilities for the cost function calculations. The algorithm further identifies a reduced set of potential candidate test points according to a variety of criteria such as cluster roots, i.e., nodes in the IC having poor controlability at the outputs but good controlability at the inputs, by considering the inputs to the cluster roots as good test point candidates. The genetic algorithm makes it a prime candidate for implementation using parallel processing, wherein multiple computers are used to simultaneously evaluate potential solutions.
A method for analyzing an integrated circuit (IC) under test and for identifying and inserting test points in order to improve the testability of the IC, the method comprising the steps of:
A method for analyzing an integrated circuit (IC) under test and for identifying and inserting potential test points in order to improve the testability of the IC, the method comprising the steps of:
The method as recited in claim 12, further comprising the step of refreshing said first plurality of sets of test points to its original state and repeating steps a) through f) to generate a total number of pairs of test point sets to be intermingled..
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for analyzing an integrated circuit (IC) under test and for identifying and inserting test points in order to improve the testability of the IC, said method steps comprising:
Dependencies are inferred from the claim text.