System and method for power saving delay locked loop control

A DRAM device comprising:

• a plurality of rows of DRAM memory cells, the DRAM memory cells receiving, storing, and outputting data;
• an input/output system operably connected to the rows of DRAM memory cells for communicating data between the rows of DRAM memory cells and an external system;
• a refresh system for refreshing contents of the DRAM memory cells;
• a control logic array, the control logic array being operably interconnected with the input/output system and responsive to command from the external system;
• and
• a delay locked loop subsystem synchronizing data communications between the input/output system and the external system, the delay locked loop having a delay locked loop control comprising:
• a device inactive decoder providing a device inactive signal when the delay locked loop need not continue adjusting a delay interval to synchronize with the system clock;
• a stabilization detection device providing a stabilization signal when the device is stable after reacting to a command applied to the device;
• and
• a delay lock coupled to the device inactive decoder and the stabilization detection device for locking the delay interval on receiving both the device inactive signal and the stabilization detection signal.

A computer system, comprising:

• a processor;
• an input device, operably connected to the processor, allowing data to be entered into the computer system;
• an output device, operably connected to the processor, allowing data to be output from the computer system;
• and
• a system memory operably connected to the processor through a system bus, the system memory comprising a plurality of DRAM devices having a plurality of rows of DRAM memory cells, the DRAM memory cells receiving, storing, and outputting data, at least one of the DRAM devices comprising:
• an input/output system operably connecting the plurality of DRAM devices the computer system;
• a refresh system for refreshing contents of the DRAM memory cells;
• control logic, the control logic being operably interconnected with the input/output system and responsive to command from the external system;
• a delay locked loop subsystem synchronizing data communications between the input/output system and the computer system;
• and
• a delay locked loop control comprising:
• a device inactive decoder providing a device inactive signal when the delay locked loop need not continue adjusting a delay interval to synchronize with the system clock;
• a stabilization detection device providing a stabilization signal when the device is stable after reacting to a command applied to the device;
• and
• a delay lock coupled to the device inactive decoder and the stabilization detection device for locking the delay interval on receiving both the device inactive signal and the stabilization detection signal.

A method for saving power in a delay locked loop associated with a device responding to a system clock, the method comprising:

• determining when it is unnecessary for the delay locked loop to adjust a delay interval to synchronize with the system clock;
• allowing the device to stabilize after receiving a command applied to the device before it was determined it is unnecessary for the delay locked loop to adjust the delay interval;
• and
• locking the delay interval when it is unnecessary for the delay locked loop to adjust the delay interval and the device has stabilized.