Method and apparatus for data transfer
AssigneeMicron Technology, Inc.
InventorPaul A. LaBerge
Life of this patent
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Abstract
A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one embodiment, the adaptive timing system comprises a delay circuit for sampling the data signal at a midpoint of the DVW. The adaptive timing system may also comprise an identifying circuit for identifying whether the midpoint of the DVW corresponds to an actual midpoint of the DVW and adjusting the delay circuit accordingly.
Claims42
A memory controller for controlling a transfer of a datum from a data source to a data destination, comprising:
- a delay circuit configured to generate a plurality of delay clock signals at different times;
- a plurality of latches responsive to the plurality of delay clock signals, wherein each latch receives a timing signal from the data source and generates a latched signal corresponding to the timing signal received from the data source in response to the delay clock signal;
- and
- a compare circuit responsive to a plurality of the latched signals from the plurality of latches, wherein the compare circuit is configured to generate a comparison signal corresponding to a difference between the plurality of the latched signals.
An electronic system, comprising:
- a data source configured to generate a data signal and a timing signal;
- a data destination;
- means for analyzing the timing signal from the data source, wherein the timing signal analyzing means identifies a data valid window (DVW) in the data signal according to the timing signal;
- means for capturing data in the DVW in the data signal from the data source;
- means for transferring the captured data to the data destination;
- and
- means for adjusting the data capturing means according to the timing signal analyzing means.
A data transfer system for transferring data from a data source to a data destination, comprising:
- a sampler configured to sample a timing signal from the data source at a plurality of times;
- and
- a compare circuit configured to analyze the samples from the sampler to identify a leading edge, a trailing edge, and a midpoint of a data valid window (DVW) in the timing signal.
A memory control system for controlling access to a memory module, comprising:
- a sampling circuit for taking samples from a timing signal;
- and
- an analysis circuit for receiving the samples from the sampling circuit and identifying a data valid window (DVW) according to the timing signal.
A memory controller for controlling transfers of data from a data source to a data destination, comprising a timing circuit for generating a capture signal, wherein the timing circuit identifies at least one of a leading edge and a trailing edge of a data valid window (DVW) of a timing signal.
A method of transferring data from a data source to a data destination, comprising:
- sampling a signal to identify at least one of an approximate leading edge and an approximate trailing edge of a data valid window (DVW);
- and
- adjusting at least one of a nominal leading edge and a nominal trailing edge of the DVW according to at least one of the identified approximate leading edge of the DVW and the identified approximate trailing edge of the DVW.
A method of transferring data from a data source to a data destination, comprising:
- sampling a timing signal from the data source;
- identifying a data valid window (DVW) in a data signal according to the sampled timing signal;
- and
- capturing the data in the identified DVW.
A method of reading data from a memory, comprising:
- requesting a timing signal from the memory;
- sampling the requested timing signal;
- identifying at least one of a leading edge and a trailing edge of a data valid window (DVW) in the timing signal;
- calculating an approximate midpoint of the DVW based on the at least one of the leading edge and the trailing edge;
- receiving a data signal from the memory;
- and
- capturing a datum from the data signal at an approximate midpoint of a DVW of the data signal corresponding to the approximate midpoint of the DVW of the timing signal.
Dependencies are inferred from the claim text.