Single chip microcomputer
OwnerYoshinori Teshima, Shuji Agatsumainventors
Life of this patent
Estimating the term…
Abstract
Disclosed is a single-chip microcomputer capable of facilitating debugging even in the case of including a plurality of CPUs. In the single-chip microcomputer 41 carrying two CPUs 41A and 41B, the CPU 42A is released from its reset condition by a power-on reset circuit 33 at power-on, while another CPU 42B is released from its reset condition through a CPU(B) reset register 44 in accordance with processing based on the control program of the CPU 42.
Claims1
A single-chip microcomputer comprising a plurality of CPUs and a program memory storing control programs for said plurality of CPUs, each of said plurality of CPUs recognizing a number allocated thereto when being released from its reset condition and reading out said control program corresponding to said number from said program memory for conducting processing,
- characterized in that one of said plurality of CPUs is released from its reset condition by a power-on reset circuit at power-on, and
- the other CPUs are released from their reset condition through processing based on said control program for said CPU released from its reset condition by said power-on reset circuit.
Dependencies are inferred from the claim text.