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US 2003/0154365 A1Published application
Power savings in dynamic register file structures
AssigneeSun Microsystems, Inc.
InventorsArjun P. Chandran, Gregg K. Tsujimoto, Anup S. Mehta
Life of this patent
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Abstract
In the Retirement Payload Array (RPA) of a microprocessor, the pointer advance signal “ADVANCE POINTER” from the Instruction Retirement Logic (IRL) of the Instruction Scheduling Unit (ISU) is utilized to provide conditional read RPA signals. Consequently, according to the invention, a read of the RPA is completed only if it is determined that the read word line being read in the current cycle is not the same read word line that was read in the previous cycle.
Claims24
A method for performing conditional reads of a retirement payload array in a microprocessor, said method comprising:
- receiving a clock signal, said clock signal having a first or “A” phase and a second or “B” phase;
- receiving an advance pointer signal, said advance pointer signal having a first or inactive phase and a second or active phase, said second or active phase of said advance pointer signal corresponding to a shift in position of a read pointer of said retirement payload array;
- initiating a read of said retirement payload array only when, both:
- said clock signal is in said “B” phase;
- and said advance pointer signal is in said active phase.
2 more elements
A method for performing conditional reads of a retirement payload array in a microprocessor, said method comprising:
- providing a retirement payload array, said retirement payload array comprising M rows of memory cells and N columns of memory cells;
- said retirement payload array further comprising M read word lines and N read bit lines, wherein, each of said N read bit lines is coupled to a corresponding pre-charge device and a corresponding sensing device;
- coupling a clock signal to said retirement payload array, said clock signal having a first or “A” phase and a second or “B” phase;
- wherein said pre-charge devices are pre-charged when said clock signal is in said first or “A” phase;
- coupling an advance pointer signal to said retirement payload array, said advance pointer signal having a first or inactive phase and a second or active phase, said second or active phase of said advance pointer signal corresponding to a shift in position of a read pointer of said retirement payload array;
- initiating a read of said retirement payload array only when, both:
- said clock signal is in said “B” phase;
- and
- said advance pointer signal is in said active phase.
6 more elements
A retirement payload array comprised of modified column structures, each of said modified column structures comprising:
- a read bit line;
- a pre-charge device coupled to said read bit line;
- a sensing device coupled to said read bit line;
- at least one memory cell, said memory cell comprising an output coupled to said read bit line and an input;
- a gate, said gate comprising an output coupled to said input of said at least one memory cell and an input;
- a conditional read circuit, said conditional read circuit comprising a first input, a second input and an output, said conditional read circuit output being coupled to said input of said gate,
- a clock signal, said clock signal having a first or “A” phase and a second or “B” phase, said clock signal being coupled to said second input of said conditional read circuit;
- an advance pointer signal, said advance pointer signal having a first or inactive phase and a second or active phase, said second or active phase of said advance pointer signal corresponding to a shift in position of a read pointer, said advance pointer signal being coupled to said first input of said conditional read circuit, wherein;
- said conditional read circuit initiates a read of said retirement payload array only when, both:
- said clock signal is in said “B” phase;
- and
- said advance pointer signal is in said active phase.
9 more elements
A retirement payload array comprised of modified column structures, each of said modified column structures comprising:
- a read bit line;
- a pre-charge device coupled to said read bit line, said pre-charge device comprising a transistor;
- a sensing device coupled to said read bit line, said sensing device comprising a latch;
- at least one memory cell, said memory cell comprising an output coupled to said read bit line and an input;
- a NOR-Gate comprising a first input, a second input and an output, said NOR-Gate output being coupled to said input of said at least one memory cell;
- a conditional read circuit, said conditional read circuit comprising:
- an inverter, said inverter having an input and an output;
- and
- a NAND-Gate having a first input, a second input, and an output, said NAND-Gate output being coupled to said NOR-Gate first input, said inverter output being coupled to said NAND-Gate second input;
- a clock signal, said clock signal having a first or “A” phase and a second or “B” phase, said clock signal being coupled to said input of said inverter of said conditional read circuit, said pre-charge devices being pre-charged when said clock signal is in said first or “A” phase;
- an advance pointer signal, said advance pointer signal having a first or inactive phase and a second or active phase, said second or active phase of said advance pointer signal corresponding to a shift in position of a read pointer, said advance pointer signal being coupled to said first input of said NAND-Gate of said conditional read circuit, wherein;
- said conditional read circuit initiates a read of said retirement payload array only when, both:
- said clock signal is in said “B” phase;
- and
- said advance pointer signal is in said active phase.
12 more elements
Dependencies are inferred from the claim text.