Instruction execution in a processor
AssigneeAlphamosaic Limited
InventorsStephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
Life of this patent
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Abstract
A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value pairs and to generate a respective result; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit.
Claims18
A processor comprising:
- a scalar processing unit for executing scalar instructions each defining a single value pair;
- a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value pairs and to generate a respective result;
- and
- an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit.
A processor according to any preceding claim, wherein the vector processing unit comprises a vector register file holding operands addressable by said vector instructions for supply to the value processing units, each operand being a packed operand comprising a plurality of values.
A processor according to any preceding claim, wherein each value pair comprises a value from each of first and second packed operands.
A processor according to any preceding claim, wherein each instruction comprises a destination address identifier, denoting a storage location for holding the result of execution of the instruction.
A processor according to any preceding claim which is a graphics processor wherein each of the values represents a pixel, whereby each value processing unit performs an operation on a pair of pixel values.
A processor according to any preceding claim, which comprises an instruction memory holding a program in the form of instructions including scalar instructions and vector instructions in a common instruction space.
A processor according to any preceding claim, which comprises a data memory holding data values.
A processor according to any preceding claim, wherein scalar instructions are encoded optionally in 16-bit, 32-bit and 48-bit forms.
A processor according to any preceding claim, wherein vector instructions are encoded optionally in 48 and 80-bit forms.
A processor according to any preceding claim, wherein vector instructions and scalar instructions each include a bit sequence at predetermined bit locations, said bit sequence being detectable by the instruction decoder to identify an instruction as a scalar instruction or a vector instruction.
A method of operating a processor having a scalar processing unit and a vector processing unit, the method comprising:
- fetching a stream of instructions including scalar instructions and vector instructions;
- decoding said instructions and supplying said scalar instructions to a scalar processing unit for execution, and said vector instructions to a vector processing unit for execution;
- in the vector processing unit, executing said vector instructions in a plurality of value processing units, each operable to process at least a pair of values defined by the vector instruction;
- and
- supplying, for at least some of said vector instructions, the results of executing said vector instructions to the scalar processing unit.
A computer program comprising a common instruction space including executable instruction streams, each instruction stream including scalar instructions and vector instructions, wherein each scalar instruction defines a single operand set and each vector instruction defines multiple operand sets, the computer program being loadable into a computer and co-operable therewith such that scalar instructions are executed by a scalar processing unit of the computer and vector instructions are executed by a vector processing unit of the computer.
Dependencies are inferred from the claim text.