Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

An integrated circuit comprising:

• an input pipeline register to receive an input data packet;
• a memory capable of storing the input data packet;
• a hardware task manager capable of processing a plurality of tasks and determining that a first task from the plurality of tasks is capable of being performed and that a second task from the plurality of tasks is capable of being performed, the first task being different than the second task;
• a data distributor coupled to the input pipeline register, to the memory, and to the hardware task manager, the data distributor capable of distributing the input data packet to the hardware task manager and further capable of distributing the input data packet to the memory;
• an adaptive execution unit coupled to the hardware task manager and to the memory, the adaptive execution unit capable of configuring to perform the first task and capable of performing the first task using the input data packet, the adaptive execution unit further capable of reconfiguring to perform the second task and capable of performing the second task, the adaptive execution unit further capable of generating an output data packet from the performance of the first task and the second task;
• a data selector coupled to the hardware task manager, to the adaptive execution unit and to the memory, the data selector capable of determining routing for the output data packet;
• and
• an output pipeline register coupled to the data selector to receive the output data packet.

An adaptive computing integrated circuit, comprising:

• a plurality of heterogeneous computational elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture;
• an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network capable of configuring the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the interconnection network further capable of reconfiguring the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information, the first functional mode being different than the second functional mode;
• and
• a fixed function node coupled to the interconnection network, the fixed function node having a third fixed architecture, the fixed function node capable of performing a predetermined application.

An integrated circuit comprising:

• an input pipeline register to receive an input data packet;
• a memory capable of storing the input data packet;
• a hardware task manager capable of processing a plurality of tasks and determining that a first task from the plurality of tasks is capable of being performed and that a second task from the plurality of tasks is capable of being performed, the first task being different than the second task;
• a data distributor coupled to the input pipeline register, to the memory, and to the hardware task manager, the data distributor capable of distributing the input data packet to the hardware task manager and further capable of distributing the input data packet to the memory;
• an adaptive execution unit coupled to the hardware task manager and to the memory, the adaptive execution unit comprising a plurality of computational elements and a plurality of switching elements coupled to the plurality of computational elements, wherein a first computational element of the plurality of computational elements has a first fixed architecture and a second computational element of the plurality of computational elements has a second fixed architecture, the first fixed architecture being different from the second fixed architecture;
• wherein the plurality of switching elements are capable of configuring the plurality of computational elements for performance of the first task in response to first configuration information, and the plurality of switching elements further capable of reconfiguring the plurality of computational elements for performance of the second task in response to second configuration information;
• and wherein the plurality of computational elements are further capable of using the input data packet and generating an output data packet from the performance of the first task and the second task;
• a data selector coupled to the hardware task manager, to the adaptive execution unit and to the memory, the data selector capable of determining routing for the output data packet;
• and
• an output pipeline register coupled to the data selector to receive the output data packet.

An adaptive computing integrated circuit, comprising:

• a plurality of heterogeneous computational elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture of a plurality of fixed architectures and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture of the plurality of fixed architectures, the first fixed architecture being different than the second fixed architecture, the plurality of fixed architectures comprising at least two of the following corresponding functions:
• memory, addition, multiplication, complex multiplication, subtraction, synchronization, queuing, over sampling, under sampling, adaptation, configuration, reconfiguration, control, input, output, and field programmability;
• an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network capable of configuring the plurality of heterogeneous computational elements for performance of a first algorithmic element of a plurality of algorithmic elements in response to first configuration information, and the interconnection network further capable of reconfiguring the plurality of heterogeneous computational elements for performance of a second algorithmic element of the plurality of algorithmic elements in response to second configuration information, the first algorithmic element being different than the second algorithmic element;
• and
• wherein the plurality of algorithmic elements comprises at least two of the following algorithmic elements:
• a radix-2 Fast Fourier Transformation (FFT), a radix-4 Fast Fourier Transformation (FFT), a one-dimensional Discrete Cosine Transformation (DCT), a multi-dimensional Discrete Cosine Transformation (DCT), finite impulse response (FIR) filtering, convolutional encoding, scrambling, puncturing, interleaving, modulation mapping, Golay correlation, OVSF code generation, Haddamard Transformation, Turbo Decoding, bit correlation, Griffiths LMS algorithm, variable length encoding, uplink scrambling code generation, downlink scrambling code generation, downlink despreading, uplink spreading, uplink concatenation, Viterbi encoding, Viterbi decoding, cyclic redundancy coding (CRC), complex multiplication, data compression, motion compensation, channel searching, channel acquisition, multipath correlation.