Methods and apparatus for cache intervention
AssigneeIntel Corporation
InventorsSujat Jamil, Hang Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven J. Tu
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AssigneeIntel Corporation
InventorsSujat Jamil, Hang Nguyen, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven J. Tu
Estimating the term…
Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds the memory block prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache regardless of the state (modified or non-modified) of the cached block. In addition, an agent associated with the first cache asserts a “hit” signal line regardless of the state (modified or non-modified) of the cached block. The agent associated with the first cache does not assert a “hit-modified” signal line.
A method comprising:
An apparatus comprising:
An apparatus comprising:
Dependencies are inferred from the claim text.