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OwnerWei Ma, Jie Liang +2inventors
InventorsWei Ma, Jie Liang, Kah Yong Lee, Kiak Wei Khoo
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A method for reducing power consumption within a processing architecture, the processing architecture including a processor and a memory device, the memory device having a memory cell, the processor having a processing element, the processor configured to read from the memory device and write to the memory device is described. The method comprises configuring the memory with logical processing circuits internal to the memory device which access the memory cell, performing logical operations to data within the memory cell utilizing the logical processing circuits within the memory device, and performing mathematical operations within the processing element of the processor. The method is embodied through a logic memory which significantly reduces power consumption of digital signal processors, microprocessors, micro-controllers or other computation engines in electronic systems. Logic memory is applicable to low power devices and system_on_a_chip (SoC) chips and is utilized in computer architecture design to improve speed and power efficiency.
A method for reducing power consumption within a processing architecture, the processing architecture including a processor and a memory device, the memory device having a memory cell, the processor having a processing element, the processor configured to read from the memory device and write to the memory device, said method comprising:
A memory device comprising:
A processing architecture, comprising:
A digital signal processor architecture comprising
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