US 2003/0154345 A1 · Multilevel cache system having unified cache tag memory

Abstract

A unified tag subsystem for a multilevel cache memory system. The unified tag subsystem receives a cache line address including a tag index portion, a high order part and an optional cache line extension field. The tag index portion indexes a tag memory which has way-specific address tags, and lower level flags. A comparator compares the high order part with each way-specific address tag to detect a match. Lower level hit logic determines a hit when comparator detects a match and the lower level flag indicates a valid lower level cache entry; and an upper level hit logic determines a higher level cache hit when the comparator detects a match and the upper level valid is set. In particular embodiments, lower level flag indicates a way of storage where associated data may be found in lower level cache data memory.

Claims12

Dependent claims

A unified tag subsystem for a multilevel cache memory system having an upper level and a lower level of cache data memory, the tag subsystem having at least a processor port for receiving a cache line address comprising a tag index portion, and a high order part, the unified tag subsystem comprising:

a unified tag memory coupled to be addressed by the tag index portion of the cache line address, the tag memory comprising at least one way-specific address tag, at least one upper level valid flag, and at least one way-specific lower level flag;
at least one first comparator coupled to compare the high order part with the at least one way-specific address tag and detect a match;
a lower level hit logic coupled to determine a lower level cache hit when the at least one first comparator detects a match, and the level flag indicates a valid entry in the lower cache;
and
an upper level hit logic coupled to determine a higher level cache hit when the at least one first comparator detects a match, and a high level valid flag is in a valid state.

2 more elements

A multilevel cache memory system having at least a processor port for receiving a cache line address comprising a tag index portion, and a high order part;

the multilevel cache memory system comprising:
a lower level cache data memory coupled to provide data to the processor port on a lower level cache hit;
an upper level cache data memory coupled to provide data to the processor port on an upper level cache hit;
a unified tag subsystem further comprising:
a tag memory coupled to be addressed by the tag index portion of the cache line address, the tag memory comprising at least one way-specific address tag field, at least one way-specific lower level flag field, and at least one way-specific upper level valid flag;
at least one comparator coupled to compare the high order part with the at least one way-specific address tag and detect a match;
a lower level hit logic coupled to determine a lower level cache hit when the at least one first comparator detects a match and the lower level flag indicates valid cache data in the lower level cache data memory;
and
an upper level hit logic coupled to determine a higher level cache hit when the at least one first comparator detects a match, and the a higher level valid flag field indicates valid cache data in a upper level cache data memory.

6 more elements

Dependencies are inferred from the claim text.

Multilevel cache system having unified cache tag memory

Life of this patent

Multilevel cache system having unified cache tag memory

Life of this patent

Abstract

Claims12