Multi-threaded multiply accumulator
AssigneeIntel Corporation
InventorsJason M. Howard, Yatin V. Hoskote, Sriram R. Vangal
Life of this patent
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Abstract
A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. The adder circuit includes intermediate registers to provide multi-threaded capability. Products interleaved in time are accumulated into separate sums simultaneously.
Claims30
A floating point accumulator circuit comprising:
- an exponent path;
- and
- a mantissa path having an output node fedback to an input node, and at least one sequential element in an internal data path.
An integrated circuit comprising:
- a multiplier coupled to receive operands and to produce a product;
- and
- a multi-threaded accumulator coupled to the multiplier to receive the product.
An accumulator circuit to accept operands from different threads interleaved in time, the accumulator having intermediate registers to simultaneously hold partial results from each of the different threads.
A multi-threaded floating point multiply-accumulator circuit comprising:
- a multiplier to produce a product;
- and
- an accumulator coupled to receive the product from the multiplier, the accumulator including sequential elements to provide a multi-threaded capability.
Dependencies are inferred from the claim text.