Method and system for processing complex numbers

A method of storing at least one complex number Z having a single base -2 binary code K(Z) and a scaling factor u, in the memory of a complex number arithmetic processor as a separate real part Xa and a separate imaginary part Xb, each of said real part Xa and said imaginary part Xb having a separate base 2 binary code, said method comprising the steps of:

• a) reading said single base −2 binary code K(Z) for said complex number Z;
• b) reading said scaling factor u;
• c) composing a base −2 binary code for said real part Xa and a base −2 binary code for a scaled imaginary part Xb by selecting alternate bits from said single base −2 binary code K(Z);
• d) converting said base −2 binary code for said real part Xa to base 2 to produce a base 2 binary code for said real part Xa;
• e) converting said base −2 binary code for said scaled imaginary part Xb to base 2 to produce a base 2 binary code for said scaled imaginary part Xb;
• f) dividing said scaled imaginary part Xb by said scaling factor u to produce said imaginary part Xb having a base 2 binary code;
• and,
• g) writing said base 2 binary code for said real part Xa and said base 2 binary code for said imaginary part Xb to said memory of said complex number arithmetic processor.

A method of performing an arithmetic operation on at least one complex number in a complex number arithmetic processor, comprising the steps of:

• a) reading at least one said complex number Z, each said complex number Z consisting of a real part Xa and an imaginary part Xb, each of said real part Xa and said imaginary part Xb having a separate base 2 binary code;
• b) reading said arithmetic operation;
• c) selecting a coding system f(p,m) having a base p, a scale factor u, and an imaginary unit w, wherein the product of said scale factor u and said imaginary unit w equals the complex unit j and wherein the complex unit j equals the square root of negative one;
• d) coding each said complex number Z to produce a single base -2 binary code K(Z) defined by said coding system f(p,m);
• e) coding said imaginary unit w to produce a single base −2 binary code K(w) defined by said coding system f(p,m);
• f) performing said arithmetic operation using said single base −2 binary code K(Z) for each complex number Z and said single base −2 binary code K(w) for said imaginary unit w, to produce at least one resultant complex number, each said resultant complex number Z′ having a single base −2 binary code K(Z′);
• and,
• g) decoding each said resultant complex number Z′ to produce a base 2 binary code for the real part Xa′ of each said resultant complex number Z′ and a base 2 binary code for the imaginary part Xb′ of each said resultant complex number Z′;
• and,
• h) storing each said base 2 binary code for the real part Xa′ and each base 2 binary code for the imaginary part Xb′ of each said resultant complex number Z′.

An adder circuit for adding a first complex number and a second complex number, said first and said second complex numbers being stored as single base −2 binary codes under a coding system f(p,m), said adder circuit having a plurality of stages, each said stage comprising:

• a first input for receiving a kth digit of said first complex number;
• a second input for receiving a kth digit of said second complex number;
• a third input for receiving a kth carry-in from a carry-out of a k−2th stage;
• a first output for providing a kth result digit;
• a second output for providing a kth carry-out;
• and, an adder for adding said kth digit of said first complex number, said kth digit of said second complex number, and said kth carry-in to provide said kth result digit and said kth carry-out.

An adder circuit for adding a first complex number and a second complex number, said first and said second complex numbers being stored as single base −2 binary codes under a coding system f(p,m), said adder circuit having a plurality of stages, each said stage comprising:

• a first input for receiving a kth digit of said first complex number;
• a second input for receiving a kth digit of said second complex number;
• a third input for receiving a first kth carry-in from a carry-out of a k−2th stage;
• a fourth input for receiving a second kth carry-in from a carry-out of a k−3th stage;
• a fifth input for receiving a third kth carry-in from a carry-out of a k−4th stage;
• a first output for providing a kth result digit;
• a second output for providing a kth carry-out;
• and, an adder for adding said kth digit of said first complex number, said kth digit of said second complex number, said first kth carry-in, said second kth carry-in, and said third kth carry-in to provide said kth result digit and said kth carry-out.

An adder circuit for adding a first complex number and a second complex number, said first and said second complex numbers being stored as single base −2 binary codes under a coding system f(p,m), said adder circuit having a plurality of stages, each said stage comprising:

• a first input for receiving a kth digit of said first complex number;
• a second input for receiving a kth digit of said second complex number;
• a third input for receiving a first kth carry-in from a carry-out of a k−1th stage;
• a fourth input for receiving a second kth carry-in from a carry-out of a k−2th stage;
• a fifth input for receiving a third kth carry-in from a carry-out of a k−3th stage;
• a first output for providing a kth result digit;
• a second output for providing a kth carry-out;
• and, an adder for adding said kth digit of said first complex number, said kth digit of said second complex number, said first kth carry-in, said second kth carry-in, and said third kth carry-in to provide said kth result digit and said kth carry-out.

A complex number arithmetic processor for performing an arithmetic operation on at least one complex number, comprising:

• a) a control unit for storing instructions;
• b) at least one first register responsive to said control unit for reading at least one said complex number Z, each said complex number Z consisting of a real part Xa and an imaginary part Xb, each of said real part Xa and said imaginary part Xb having a separate base 2 binary code;
• c) at least one second register responsive to said control unit for reading said arithmetic operation;
• d) said control unit being operative to select a coding system f(p,m) having a base p, a scale factor u, and an imaginary unit w, wherein the product of said scale factor u and said imaginary unit w equals the complex unit j and wherein the complex unit j equals the square root of negative one;
• e) at least one first encoder responsive to said control unit for coding each said complex number Z to produce a single base −2 binary code K(Z) defined by said coding system f(p,m);
• f) at least one second encoder responsive to said control unit for coding said imaginary unit w to produce a single base −2 binary code K(w) defined by said coding system f(p,m);
• g) said control unit being operative to perform said arithmetic operation using said single base −2 binary code K(Z) for each complex number Z and said single base −2 binary code K(w) for said imaginary unit w, to produce at least one resultant complex number, each said resultant complex number Z′ having a single base −2 binary code K(Z′);
• and,
• h) at least one decoder responsive to said control unit for decoding each said resultant complex number Z′ to produce a base 2 binary code for the real part Xa′ of each said resultant complex number Z′ and a base 2 binary code for the imaginary part Xb′ of each said resultant complex number Z′;
• and,
• i) at least one third register responsive to said control unit for storing each said base 2 binary code for the real part Xa′ and each base 2 binary code for the imaginary part Xb′ of each said resultant complex number Z′.