Method of manufacturing a semiconductor integrated circuit device

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming a first wiring having a first conductive film and a second conductive film thereon in a chip area of a semiconductor wafer, and forming a pattern for test having the first conductive film and the second conductive film thereon in a scribe area of the semiconductor wafer;
• (b) forming a first insulating film on the first wiring and the pattern for test;
• (c) removing the portions of the first insulating film on the first wiring and the pattern for test, and thereby exposing a first pad area;
• (d) forming a second wiring extending from the first pad area as the top of the first wiring to a second pad area;
• (e) forming a second insulating film on the second wiring and the pattern for test;
• (f) removing the portions of the second insulating film on the second pad portion of the second wiring and the scribe area;
• and
• (g) cleaning the semiconductor wafer subsequent to the step (f).

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming a first wiring having a first conductive film and a second conductive film thereon in a chip area of a semiconductor wafer, and forming a pattern for test having the first conductive film and the second conductive film thereon in a scribe area of the semiconductor wafer;
• (b) forming a second wiring on the first wiring via an insulating film;
• and
• (c) forming a plated film on a pad area which is a part of the second wiring with the second conductive film as the surface of the pattern for test being exposed.

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming a first wiring having a first conductive film and a second conductive film thereon in a chip area of a semiconductor wafer, and forming a pattern for test having the first conductive film and the second conductive film thereon in a scribe area of the semiconductor wafer;
• (b) forming a first insulating film on the first wiring and the pattern for test;
• and
• (c) removing the portions of the first insulating film on the first wiring and the pattern for test, and thereby exposing a first pad area;
• (d) forming a second wiring extending from the first pad area as the top of the first wiring to a second pad area;
• (e) forming a second insulating film on the second wiring and the pattern for test;
• (f) removing the portions of the second insulating film on the second pad portion of the second wiring and the scribe area;
• and
• (g) forming a plated film on the pad area which is a part of the second wiring, subsequent to the step (f).

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming a first wiring electrically connected to a semiconductor element formed on a semiconductor wafer;
• (b) forming a first conductive film on a pad area which is a part of the first wiring;
• (c) subjecting the semiconductor wafer to a heat treatment subsequent to the step (b);
• (d) testing the characteristics of the semiconductor element by utilizing the pad area subsequent to the step (c);
• (e) further forming a second conductive film on the first conductive film subsequent to the step (d);
• and
• (f) forming a bump electrode on the second conductive film.

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming a wiring electrically connected to a non-volatile memory formed on a semiconductor substrate in wafer form;
• (b) forming, on the wiring, a polyimide film having an opening on a pad area of the wiring;
• and
• (c) applying, subsequent to the step (b), a heat load to the semiconductor substrate in wafer form for a given time period, and testing the information retention characteristics of the non-volatile memory by utilizing the pad area.

A method of manufacturing a semiconductor integrated circuit devices comprising the steps of:

• (a) forming a wiring electrically connected to a non-volatile memory formed on a semiconductor substrate in wafer form;
• (b) forming, on the wiring, a polyimide film having an opening on a pad area of the wiring;
• (c) applying, subsequent to the step (b), a heat load to the semiconductor substrate in wafer form for a given time period, and testing the information retention characteristics of the non-volatile memory by utilizing the pad area;
• and
• (d) forming a plated film on the pad area subsequent to the step (c).