Ball grid array package for enhanced stress tolerance

A semiconductor assembly comprising:

• a substrate comprising a support of electrically insulating material having a first and a second surface;
• a plurality of electrically conductive routing strips integral with said substrate;
• a plurality of contact pads disposed in a pattern on said first surface and connected to said routing strips, said pads having a composition suitable for solder attachment;
• said first surface covered by an adherent, sheet-like elastic polymer, said polymer being non-wettable by solder and having a coefficient of volumetric shrinkage greater than solder;
• said polymer sheet having openings exposing each of said contact pads, the walls of said openings tapering towards said pads;
• an integrated circuit chip attached to said second substrate surface;
• solder connections reflowed onto said contact pads such that said solder connections, upon cooling, are shaped in column-like contours and separated from said walls by a gap, whereby each said column-like connection has sufficient length after board attach to act as a stress-distributing joint.

A process for fabricating an interconnection substrate for use in semiconductor assembly, comprising the steps of:

• providing a support of electrically insulating material having a plurality of contact pads disposed on the surface of said support, said pads having a composition suitable for solder attachment;
• providing a sheet-like elastic polymer non-wettable by solder and having a coefficient of volumetric shrinkage greater than solder, said sheet having a plurality of openings in a pattern matching the pattern of said contact pads;
• aligning said polymer sheet with said support such that each of said openings is placed into alignment with one said contact pads;
• and
• attaching said polymer sheet to said support surface using elevated temperature, thereby selectively exposing said contact pads and tapering the walls of said openings towards said pads.

A process for fabricating a semiconductor assembly comprising the steps of:

• providing a substrate having an electrically insulating support with first and second surfaces and a plurality of routing strips integral with said substrate, said first surface having a plurality of contact pads suitable for solder attachment and further covered by a sheet-like elastic polymer, non-wettable by solder and having a coefficient of volumetric shrinkage greater than solder, said sheet having openings exposing each of said pads, the walls of said openings tapered towards said pads;
• attaching an integrated circuit chip to said second substrate surface;
• electrically connecting said chip to said second surface using bonding wires;
• surrounding said chip and said bonding wires with an encapsulation compound;
• positioning one solder ball in each of said openings;
• elevating the temperature to reflow said solder, thereby attaching said solder to said pad metallization while not wetting said polymer walls;
• and
• lowering said reflow temperature to room temperature, thereby volumetrically shrinking said polymer more than said solder, thus creating a gap between said solder and said opening walls and shaping said solder into column-like contours.

A process for fabricating a semiconductor assembly comprising the steps of:

• providing a substrate having an electrically insulating support with first and second surfaces and a plurality of routing strips integral with said substrate, said first and second surfaces having a plurality of contact pads suitable for solder attachment, said first surface further covered by a sheet-like elastic polymer non-wettable by solder and having a coefficient of volumetric shrinkage greater than solder, said sheet having openings exposing each of said pads, the walls of said openings tapering towards said pads;
• attaching and electrically connecting an integrated circuit chip to said contact pads on said second substrate surface using chip solder bumps in flip process;
• positioning one solder ball in each of said openings;
• elevating the temperature to reflow said solder, thereby attaching said solder to said pad metallization while not wetting said polymer walls;
• and
• lowering said reflow temperature to room temperature, thereby volumetrically shrinking said polymer more than said solder, thus creating a gap between said solder and said opening walls and shaping said solder into column-like contours.

A process for fabricating a semiconductor assembly comprising the steps of:

• providing a substrate having an electrically insulating support with first and second surfaces and a plurality of routing strips integral with said substrate, said first and second surfaces having a plurality of contact pads suitable for solder attachment;
• attaching and electrically connecting an integrated circuit chip to said contact pads on said second substrate surface using chip solder bumps in flip process;
• providing a sheet-like elastic polymer non-wettable by solder and having a coefficient of volumetric shrinkage greater than solder, said sheet having a plurality of openings in a pattern matching the pattern of said contact pads on said first substrate surface;
• aligning said polymer sheet with said substrate such that each of said openings is placed into alignment with one said contact pad on said first substrate surface;
• attaching said polymer sheet to said first substrate surface using elevated temperature, thereby selectively exposing said contact pads and tapering the walls of said openings towards said pads;
• positioning one solder ball in each said opening;
• elevating the temperature to reflow said solder, thereby attaching said solder to said pad metallization while not wetting said polymer walls;
• and
• lowering said reflow temperature to ambient temperature, thereby volumetrically shrinking said polymer more than said solder, thus creating a gap between said solder and said opening walls and shaping said solder into column-like contours.