Back to results
US 2003/0153156 A1Published application
Logic array and dynamic logic method
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input. A logic gate array comprises a plurality of vertical ultrathin transistors coupled together.
Claims49
A monotonic dynamic-static pseudo-NMOS logic circuit comprising:
- a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input;
- and
- a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input, the static logic circuit having a logic input coupled to the output of the dynamic logic circuit.
A monotonic dynamic-static pseudo-NMOS logic circuit comprising:
- a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input;
- and
- a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input, the static logic circuit having a logic input coupled to the output of the dynamic logic circuit, the static logic circuit including a p-type transistor having a control electrode defining the clock input and having a channel extending between a voltage supply and the output of the static logic circuit.
A monotonic dynamic-static pseudo-NMOS logic circuit comprising:
- a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input;
- and
- a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input, the static logic circuit having a logic input coupled to the output of the dynamic logic circuit, the static logic circuit including a p-type transistor having a control electrode defining the clock input, having a channel extending between a voltage supply and the output of the static logic circuit, and having logic circuitry, configured to define a logic function, coupled between a low voltage and the output configured to be precharged low, wherein the logic circuitry configured to define a logic function includes a plurality of transistors, the transistors of the logic circuitry configured to define a logic function consisting essentially of n-type transistors having respective gates, one of which defines the clock bar input and the rest of which define inputs to the logic circuitry.
A monotonic dynamic-static pseudo-NMOS logic circuit comprising:
- a static logic circuit having a clock bar input and having an output configured to be precharged low when a low clock signal is provided to the clock bar input;
- and
- a dynamic logic circuit having a clock input, having an output configured to be precharged high when a low clock signal is provided to the clock input, having a logic input coupled to the output of the static logic circuit, and having a p-type transistor including a control electrode defining the clock input, including a power electrode coupled to the voltage supply, and including a power electrode coupled to the output of the dynamic logic circuit.
A monotonic dynamic-static pseudo-NMOS logic circuit comprising:
- a static logic circuit having a clock bar input and having an output configured to be precharged low when a low clock signal is provided to the clock bar input;
- and
- a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input, the dynamic logic circuit having a logic input coupled to the output of the static logic circuit.
A monotonic dynamic-static pseudo-NMOS logic circuit comprising:
- a static logic circuit having a clock bar input and having an output configured to be precharged low when a low clock signal is provided to the clock bar input, the static logic circuit further having logic circuitry, configured to define a logic function, coupled between a low voltage and the output configured to be precharged low, the logic circuitry configured to define a logic function of the static logic circuit including a plurality of transistors, the transistors of the logic circuitry configured to define a logic function consisting essentially of n-type transistors, the n-type transistors having respective gates, one of which defines the clock bar input and the rest of which define inputs to the logic circuitry;
- and
- a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input, the dynamic logic circuit having a logic input coupled to the output of the static logic circuit.
A method comprising:
- coupling the output of a dynamic logic circuit to a logic input of a static logic circuit, the dynamic logic circuit having a clock input;
- the static logic circuit having a clock bar input and having an output;
- pre-charging high the output of the dynamic logic circuit when a low clock signal is provided to the clock input;
- and
- precharging low the output of the static logic circuit when a high value of the complement of the clock signal is provided to the clock bar input.
2 more elements
A method comprising:
- coupling the output of a static logic circuit to a logic input of a dynamic logic circuit, the dynamic logic circuit having a clock input;
- the static logic circuit having a clock bar input and having an output;
- pre-charging high the output of the dynamic logic circuit when a low clock signal is provided to the clock input;
- and
- precharging low the output of the static logic circuit when a high value of the complement of the clock signal is provided to the clock bar input.
2 more elements
A logic gate array comprising a plurality of vertical ultrathin transistors coupled together.
A method of forming a logic gate array comprising:
- providing a substrate having a generally planar working surface;
- oxidizing the substrate;
- forming a pillar of semiconductor material extending outwardly from the working surface of the substrate, the pillar having a plurality of sidewalls;
- depositing polysilicon over the pillars;
- directionally etching the deposited polysilicon;
- heating to cause lateral epitaxial solid phase regrowth vertically to form a thin film defining first and second source/drain regions of a transistor;
- forming a gate insulator on the thin film;
- and
- forming a gate structure relative to the thin film.
6 more elements
A method of forming a logic gate array comprising:
- providing a substrate having a generally planar working surface;
- forming a plurality of pillars of semiconductor material extending outwardly from a working surface of the substrate, the pillar having a plurality of sides;
- and
- forming a plurality of vertical transistors having first and second source/drain regions formed within one of the pillars and having a gate associated with a side of that pillar, wherein one of the vertical transistors is a PMOS transistor and another of the transistors is an NMOS transistor.
1 more element
Dependencies are inferred from the claim text.