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US 2003/0153155 A1Published application
Fet having epitaxial silicon growth
AssigneeMicron Technology, Inc.
InventorsZhongze Wang, Chih-Chen Cho, Er-Xuan Ping
Life of this patent
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Abstract
Field-effect transistors, and methods of their fabrication, having channel regions formed separately from their source/drain regions and having monocrystalline material interposed between the channel regions and the source/drain regions. The monocrystalline material includes monocrystalline silicon and silicon-germanium alloy.
Claims59
A method of forming a field-effect transistor, comprising:
- forming a channel region within a bulk semiconductor material of a semiconductor substrate, wherein the channel region comprises a first monocrystalline material;
- exposing a portion of the first monocrystalline material to a surface of the semiconductor substrate;
- performing an epitaxial deposition upon the exposed portion of the first monocrystalline material, thereby forming extensions of second monocrystalline material;
- and
- forming source/drain regions on opposing sides of the channel region, wherein the source/drain regions are in contact with the extensions of second monocrystalline material.
2 more elements
A method of forming a field-effect transistor, comprising:
- forming extensions of monocrystalline material interposed between source/drain regions of the field-effect transistor and a channel region of the field-effect transistor.
A method of forming a field-effect transistor, comprising:
- forming extensions of monocrystalline silicon interposed between polycrystalline silicon source/drain regions of the field-effect transistor and a monocrystalline silicon channel region of the field-effect transistor.
A method of forming a field-effect transistor, comprising:
- forming extensions of silicon-germanium alloy interposed between polycrystalline silicon source/drain regions of the field-effect transistor and a monocrystalline silicon channel region of the field-effect transistor.
A method of forming a field-effect transistor, comprising:
- performing an epitaxial silicon growth subsequent to forming a channel region of the field-effect transistor and prior to forming source/drain regions of the field-effect transistor;
- wherein the epitaxial silicon is grown on exposed portions of monocrystalline silicon to form the epitaxial silicon interposed between the channel region and the source/drain regions.
A method of forming a field-effect transistor, comprising:
- performing an epitaxial growth of silicon-germanium alloy subsequent to forming a channel region of the field-effect transistor and prior to forming source/drain regions of the field-effect transistor;
- wherein the epitaxial growth of silicon-germanium alloy is grown on exposed portions of monocrystalline silicon to form the silicon-germanium alloy interposed between the channel region and the source/drain regions.
A method of forming a field-effect transistor, comprising:
- forming a region of monocrystalline silicon to define a channel region;
- exposing a portion of the region of monocrystalline silicon;
- growing epitaxial monocrystalline silicon from the exposed portion of the region of monocrystalline silicon;
- and
- forming a region of polycrystalline silicon in contact with the epitaxial monocrystalline silicon to define a source/drain region.
2 more elements
A method of forming a field-effect transistor, comprising:
- forming a region of monocrystalline silicon to define a channel region;
- exposing a portion of the region of monocrystalline silicon;
- growing epitaxial silicon-germanium alloy from the exposed portion of the region of monocrystalline silicon;
- and
- forming a region of polycrystalline silicon in contact with the epitaxial silicon-germanium alloy to define a source/drain region.
2 more elements
A method of forming a field-effect transistor, comprising:
- forming a first trench in a bulk semiconductor substrate on a first side of a channel region within the bulk semiconductor substrate;
- forming a second trench in the bulk semiconductor substrate on a second side of the channel region within the bulk semiconductor substrate;
- forming a layer of dielectric material within each trench;
- removing a portion of the layer of dielectric material to define a first source/drain void in the first trench and a second source/drain void in the second trench and to expose a portion of the bulk semiconductor substrate in each source/drain void;
- forming extensions of monocrystalline material on the exposed portions of the bulk semiconductor substrate in each source/drain void;
- forming source/drain semiconductive material within each source/drain void and to be in contact with the extensions of monocrystalline material;
- and
- forming a gate over the channel region.
5 more elements
A method of forming a field-effect transistor, comprising:
- forming a first trench in a monocrystalline silicon substrate on a first side of a channel region within the monocrystalline silicon substrate;
- forming a second trench in the monocrystalline silicon substrate on a second side of the channel region within the monocrystalline silicon substrate;
- forming a layer of dielectric material within each trench;
- removing a portion of the layer of dielectric material to define a first source/drain void in the first trench and a second source/drain void in the second trench and to expose a portion of the monocrystalline silicon substrate in each source/drain void;
- forming extensions of monocrystalline silicon on the exposed portions of the monocrystalline silicon substrate in each source/drain void;
- and
- forming polycrystalline silicon within each source/drain void and to be in contact with the extensions of monocrystalline silicon;
- and
- forming a gate over the channel region.
6 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon interposed between the channel region and each source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region.
4 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon interposed between the channel region and each source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region and extending beneath at least a portion of the extension of epitaxial silicon interposed between the first source/drain region and the channel region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region and extending beneath at least a portion of the extension of epitaxial silicon interposed between the second source/drain region and the channel region.
4 more elements
A field-effect transistor, comprising:
- a channel region in a monocrystalline silicon substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- epitaxial silicon formed on the monocrystalline silicon substrate between the channel region and the source/drain regions;
- and
- a gate overlying the channel region.
3 more elements
A field-effect transistor, comprising:
- a channel region in a monocrystalline silicon substrate;
- a first polycrystalline silicon source/drain region on a first side of the channel region;
- a second polycrystalline silicon source/drain region on a second side of the channel region;
- epitaxial silicon interposed between the channel region and each source/drain region;
- and
- a gate overlying the channel region.
3 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon interposed between the channel region and each source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region.
9 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon interposed between the channel region and each source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region and extending beneath at least a portion of the extension of epitaxial silicon interposed between the first source/drain region and the channel region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region and extending beneath at least a portion of the extension of epitaxial silicon interposed between the second source/drain region and the channel region.
9 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a monocrystalline silicon substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- and
- epitaxial silicon formed on the monocrystalline silicon substrate between the channel region and the source/drain regions.
7 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first polycrystalline silicon source/drain region coupled to a bit line and a second polycrystalline source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a monocrystalline silicon substrate with the first polycrystalline silicon source/drain region on a first side of the channel region and the second polycrystalline silicon source/drain region on a second side of the channel region;
- and
- epitaxial silicon interposed between the channel region and each source/drain region.
7 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- an extension of silicon-germanium alloy interposed between the channel region and each source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region.
4 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- an extension of silicon-germanium alloy interposed between the channel region and each source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region and extending beneath at least a portion of the extension of silicon-germanium alloy interposed between the first source/drain region and the channel region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region and extending beneath at least a portion of the extension of silicon-germanium alloy interposed between the second source/drain region and the channel region.
4 more elements
A field-effect transistor, comprising:
- a channel region in a monocrystalline silicon substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- epitaxial silicon-germanium alloy formed on the monocrystalline silicon substrate between the channel region and the source/drain regions;
- and
- a gate overlying the channel region.
3 more elements
A field-effect transistor, comprising:
- a channel region in a monocrystalline silicon substrate;
- a first polycrystalline silicon source/drain region on a first side of the channel region;
- a second polycrystalline silicon source/drain region on a second side of the channel region;
- epitaxial silicon-germanium alloy interposed between the channel region and each source/drain region;
- and
- a gate overlying the channel region.
3 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon-germanium alloy interposed between the channel region and each source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region.
9 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon-germanium alloy interposed between the channel region and each source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region and extending beneath at least a portion of the extension of epitaxial silicon-germanium alloy interposed between the first source/drain region and the channel region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region and extending beneath at least a portion of the extension of epitaxial silicon-germanium alloy interposed between the second source/drain region and the channel region.
9 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a monocrystalline silicon substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- and
- epitaxial silicon-germanium alloy formed on the monocrystalline silicon substrate between the channel region and the source/drain regions.
7 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first polycrystalline silicon source/drain region coupled to a bit line and a second polycrystalline source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a monocrystalline silicon substrate with the first polycrystalline silicon source/drain region on a first side of the channel region and the second polycrystalline silicon source/drain region on a second side of the channel region;
- and
- epitaxial silicon-germanium alloy interposed between the channel region and each source/drain region.
7 more elements
Dependencies are inferred from the claim text.