Back to results
US 2003/0153140 A1Published application
Methods and apparatus for adaptively adjusting a data receiver
AssigneeMicron Technology, Inc.
InventorBrent Keeth
Life of this patent
Estimating the term…
Abstract
Offsets and timing skews in data signals captured in a data receiver are reduced by adaptively adjusting a transition threshold of the data receiver. A data corrector provides a set of adjustment vectors for adjusting the transition threshold of the data receiver. The data corrector uses differential clock signals and a reference voltage to generate the set of adjustment vectors to be provided to the data receivers. The data receiver is an improved receiver incorporating a trip point adjustor that receives the set of adjustment vectors from the data corrector to adjust its trip point relative to the reference voltage.
Claims64
An electronic device comprising:
- a data receiver having a trip point adjustor;
- and
- a data corrector coupled to the data receiver for adaptively providing trip point adjustment information to the trip point adjustor.
An electronic device comprising:
- a plurality of data receivers, each data receiver having a trip point adjustor;
- and
- a data corrector coupled to each data receiver for adaptively providing trip point adjustment information to the trip point adjustor of each data receiver, the data corrector comprising:
- a first ancillary data receiver having a first trip point adjustor;
- a second ancillary data receiver having a second trip point adjustor;
- a corrector controller coupled to the first trip point adjustor of the first ancillary data receiver and coupled to the second trip point adjustor of the second ancillary data receiver for adaptively providing trip point adjustment vectors.
3 more elements
An integrated circuit comprising:
- a data receiver having a trip point adjustor;
- and
- a data corrector coupled to the data receiver for adaptively providing trip point adjustment signals to the trip point adjustor.
An integrated circuit comprising:
- a first transistor pair having a first p-type MOS transistor coupled to a first n-type MOS transistor at a first node, a gate of the first p-type MOS transistor coupled to a gate of the first n-type MOS transistor;
- a second transistor pair having a second p-type MOS transistor coupled to a second n-type MOS transistor at a second node, a gate of the second p-type MOS transistor coupled to a gate of the second n-type MOS transistor, the second p-type MOS transistor of the second transistor pair coupled to the first p-type MOS transistor of the first transistor pair at a third node, the second n-type MOS transistor of the second transistor pair coupled to the first n-type MOS transistor of the first transistor pair at a fourth node;
- a third p-type MOS transistor coupled to the third node;
- a third n-type MOS transistor coupled between the fourth node and ground having a gate coupled to a gate of the third p-type MOS transistor at the first node;
- a plurality of series configured n-type MOS transistor pairs coupled between the first node and ground;
- and
- a plurality of series configured p-type MOS transistor pairs coupled between a first voltage and the first node, wherein activating the plurality of series configured n-type MOS transistor pairs and the plurality of series configured p-type MOS transistor pairs adjusts a voltage at the first node.
4 more elements
A memory device comprising:
- a data receiver having a trip point adjustor;
- and
- a data corrector coupled to the data receiver for adaptively providing trip point adjustment information to the trip point adjustor of the data receiver.
A memory device comprising:
- a plurality of data receivers, each data receiver having a trip point adjustor;
- and
- a data corrector coupled to each data receiver for adaptively providing trip point adjustment information to the trip point adjustor of each data receiver, the data corrector comprising:
- a first ancillary data receiver having a first trip point adjustor;
- a second ancillary data receiver having a second trip point adjustor;
- a phase detector coupled to an output of the first ancillary data receiver and coupled to an output of the second ancillary data receiver, wherein the phase detector compares an output signal of the first ancillary data receiver with an output signal from the second ancillary data receiver;
- and
- a corrector controller coupled to the phase detector for receiving comparison information, the corrector controller coupled to the first trip point adjustor of the first ancillary data receiver and coupled to the second trip point adjustor of the second ancillary data receiver for adaptively providing trip point adjustment vectors.
5 more elements
A data receiver comprising:
- a receiver having a trip point;
- and
- a trip point adjustor coupled to the receiver for adaptively adjusting the trip point of the receiver.
A data receiver comprising:
- a first transistor pair having a first p-type MOS transistor coupled to a first n-type MOS transistor at a first node, a gate of the first p-type MOS transistor coupled to a gate of the first n-type MOS transistor;
- a second transistor pair having a second p-type MOS transistor coupled to a second n-type MOS transistor at a second node, a gate of the second p-type MOS transistor coupled to a gate of the second n-type MOS transistor, the second p-type MOS transistor of the second transistor pair coupled to the first p-type MOS transistor of the first transistor pair at a third node, the second n-type MOS transistor of the second transistor pair coupled to the first n-type MOS transistor of the first transistor pair at a fourth node;
- a third p-type MOS transistor coupled to the third node;
- a third n-type MOS transistor coupled between the fourth node and ground having a gate coupled to a gate of the third p-type MOS transistor at the first node;
- a plurality of series configured n-type MOS transistor pairs coupled between the first node and ground;
- and
- a plurality of series configured p-type MOS transistor pairs coupled between a first voltage and the first node, wherein activating the plurality of series configured n-type MOS transistor pairs and the plurality of series configured p-type MOS transistor pairs adjusts a voltage at the first node.
4 more elements
A trip point adjustor comprising:
- a plurality of series configured n-type MOS transistor pairs coupled between a node and ground;
- and
- a plurality of series configured p-type MOS transistor pairs coupled between a first voltage and the node, wherein activating the plurality of series configured n-type MOS transistor pairs and the plurality of series configured p-type MOS transistor pairs adjusts a voltage at the node.
A data corrector comprising:
- a first ancillary data receiver;
- a second ancillary data receiver;
- and
- a corrector controller coupled to the first ancillary data receiver and coupled to the second ancillary data receiver for adaptively providing adjustment vectors to the first ancillary data receiver and to the second ancillary data receiver.
1 more element
A data corrector comprising:
- a first ancillary data receiver having a first trip point adjustor;
- a second ancillary data receiver having a second trip point adjustor;
- a phase detector coupled to an output of the first ancillary data receiver and coupled to an output of the second ancillary data receiver, wherein the phase detector compares an output signal of the first ancillary data receiver with an output signal from the second ancillary data receiver;
- and
- a corrector controller coupled to the phase detector for receiving comparison information, the corrector controller coupled to the first and second trip point adjustors for adaptively providing trip point adjustment vectors to the first trip point adjustor and to the second trip point adjustor.
2 more elements
A phase detector comprising:
- a means for balancing two signals;
- and
- a means for comparing a zero crossing of the two signals, the means for balancing two signals coupled to the means for comparing a zero crossing of the two signals.
A balancing circuit for balancing two signals comprising:
- a first NAND gate having an output;
- a second NAND gate having an output;
- a first n-type capacitor coupled between ground and the output of the first NAND gate;
- a second n-type capacitor coupled between ground and the output of the second NAND gate;
- a first inverter coupled to the output of the first NAND gate;
- a second inverter coupled to the output of the second NAND gate;
- a third n-type capacitor coupled between ground and an output of the first inverter;
- a fourth n-type capacitor coupled between ground and an output of the second inverter;
- and
- a p-type capacitor coupled between a voltage and the output of the first inverter, wherein the n-type and p-type capacitors have capacitances set such that, for a first clock signal at an input to the first NAND gate and a second clock signal at an input to the second NAND gate, a rise time and a fall time for the first clock at an output of the first inverter is approximately equal to a rise time and a fall time for the second clock at an output of the second inverter.
7 more elements
A phase detection circuit for comparing a zero crossing of two signals comprising:
- a NAND gate having an output coupled to a first inverter;
- and
- a NOR gate having an output coupled to a second inverter, the second inverter having an output coupled to an input of the NAND gate, an input of the NOR gate coupled to an output of the first inverter.
A processing system comprising:
- a processor;
- and
- a memory device coupled to the processor, the memory device comprising:
- a plurality of data receivers, each data receiver having a trip point adjustor;
- and
- a data corrector coupled to each data receiver for adaptively providing trip point adjustment information to the trip point adjustor of each data receiver.
3 more elements
A method of operating a data receiver having a data offset adjustment comprising:
- providing a data signal to the data receiver;
- providing clock signals to a data corrector;
- generating adjustment information in the data corrector related to the received clock signals;
- and
- conditionally sending the adjustment information to the data receiver.
2 more elements
A method of operating a data corrector comprising:
- providing a first clock signal to a data port of a first ancillary data receiver, the first ancillary data receiver providing an output signal related to the first clock signal;
- providing a second clock signal to a data port of a second ancillary data receiver, the second ancillary data receiver providing an output signal related to the second clock signal;
- determining a difference between the output signals of the first and second ancillary data receivers;
- and
- generating adjustment vectors correlated to the difference between the output signals of the first and second ancillary data receivers.
2 more elements
A method for operating a memory device having data receivers with data offset adjustment comprising:
- providing a data signal to a data receiver;
- providing a first clock signal to a data port of a first ancillary data receiver, the first ancillary data receiver having a first trip point, the first ancillary data receiver providing an output signal related to the first clock signal;
- providing a second clock signal to a data port of a second ancillary data receiver, the second ancillary data receiver having a second trip point, the second ancillary data receiver providing an output signal related to the second clock signal;
- determining a difference between the output signals of the first and second ancillary data receivers;
- generating adjustment vectors correlated to the difference between the output signals of the first and second ancillary data receivers;
- providing the adjustment vectors to the first and second ancillary data receivers to adjust the trip points of the first and second ancillary data receivers;
- and
- conditionally sending the adjustment vectors to the data receiver.
5 more elements
Dependencies are inferred from the claim text.