US 2003/0153105 A1 · Integrated circuit testing with a visual indicator

Abstract

Wafer level testing is accomplished by using a visual indicator (43) in lieu of a probe machine. Before singulation, each die (52) in a wafer (50) is placed into a test mode and BIST circuitry (39) in each die performs predetermined tests of the other circuits on the die. A pass/fail signal is communicated to a visual indicating device, such as an LED, on the wafer. Each die has a corresponding visual indicator. The LED may be contained either on the die or in the scribe area. Multiple LEDs may be used for multiple circuit modules under test. The test permits easy detection of failures without using probing. Testing such as burn-in may be performed to determine whether a part will survive a range of operating conditions. In one form, a CMOS implementation of an LED may be used in conjunction with a CMOS wafer.

Claims19

Dependent claims

A method for testing an integrated circuit, comprising:

providing a wafer having multiple die that are separated by a singulation area;
providing a visual functional indicator for each of some or all of the multiple die;
providing test circuitry for each of the some or all of the multiple die that have a visual functional indicator;
powering up the wafer to electrically activate the multiple die and initiate operation of the test circuitry;
performing predetermined tests with the test circuitry for the some or all of the multiple die;
outputting a test result to the visual functional indicator for the some or all of the multiple die;
and
using the test result to create a visual indication on the wafer with each visual functional indicator corresponding to the test result.

5 more elements

Dependencies are inferred from the claim text.

Integrated circuit testing with a visual indicator

Life of this patent

Integrated circuit testing with a visual indicator

Life of this patent

Abstract

Claims19