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US 2003/0152188 A1Published application
System and method for automatic generation of an at-speed counter
AssigneeSun Microsystems, Inc.
InventorsKamran Zarrineh, Kenneth A. House, Joseph R. Siegel
Life of this patent
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Abstract
Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described
Claims24
A counter for counting cycles of a processor clock comprising
- a fast counter coupled to the processor clock via at least one first clock input, said fast counter incrementing by one after every cycle of the processor clock up to a maximum count;
- and
- a slow counter coupled to said fast counter and to at least one second clock input, wherein the slow counter increments by one after one cycle of the processor clock after the fast counter reaches the maximum count.
A method for counting cycles of a processor clock comprising
- coupling a fast counter to the processor clock via at least one first clock input;
- incrementing the fast counter by one after every cycle of the processor clock up to a maximum count;
- coupling a slow counter to said fast counter and to at least one second clock input;
- and
- incrementing the slow counter by one after one cycle of the processor clock after the fast counter reaches the maximum count.
2 more elements
A computer-readable medium that stores a program for generating a counter for counting cycles of a processor clock, the program comprising
- a fast counter generator for generating a fast counter coupled to the processor clock via at least one first clock input, said fast counter incrementing by one after every cycle of the processor clock up to a maximum count;
- and
- a slow counter generator for generating a slow counter coupled to said fast counter and to at least one second clock input, wherein the slow counter increments by one after one cycle of the processor clock after the fast counter reaches the maximum count.
Dependencies are inferred from the claim text.