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US 2003/0152162 A1Published application
Transmitter, receiver, and methods
AssigneeSony Corporation
InventorToshiaki Kojima
Life of this patent
Estimating the term…
Abstract
A computer capable of performing communications processing using a protocol at high speed in simple and low cost configuration is provided. After an SD-RAM controller stores AV data inputted via an AV interface in an AV buffer circuit, a packet processing unit, for example, generates jumbo packet data of 32 KB. A PCI bus interface outputs data required for transmitting processing of the jumbo packet data to a CPU, and the CPU generates header data. A packet processing unit, according to the header data, splits the jumbo packet data and generates Ethernet packet data of a maximum of 1518 byte. The SD-RAM controller transmits the applicable data from a MAC circuit.
Claims15
A transmitter comprising:
- a data generating circuit generating first module data including first contents data;
- an arithmetic circuit input/output interface outputting data required for transmitting processing of said first module data to an arithmetic circuit operating according to a preset program, and inputting first control data in response to a result of said transmitting processing of said first module data from said arithmetic circuit;
- a data split circuit generating second control data based on said first control data, generating a plurality of second contents data by splitting said first module data, and generating a plurality of second module data respectively including said second contents data and said second control data;
- and
- a transmission interface transmitting said second module data.
2 more elements
A transmitter comprising:
- a data generating circuit generating first module data including first contents data;
- an arithmetic circuit operating according to a preset program, performing transmitting processing of said first module data, and generating first control data in response to a result of said transmitting processing;
- an arithmetic circuit input/output interface outputting data required for said transmitting processing of said first module data to an arithmetic circuit, and inputting said first control data from said arithmetic circuit;
- a data split circuit generating second control data based on said first control data, generating a plurality of second contents data by splitting said first module data, and generating a plurality of second module data respectively including said second contents data and said second control data;
- a transmission memory circuit storing said plurality of second module data;
- and
- a transmission interface transmitting said second module data read from said transmission memory circuit.
4 more elements
A receiver comprising:
- an arithmetic circuit input/output interface outputting data required for receiving processing of first module data including first contents data and first control data to an arithmetic circuit operating according to a preset program, and inputting a result of said receiving processing from said arithmetic circuit;
- a data reassemble/split circuit generating said first module data by reassembling a plurality of received second module data respectively including second contents data and second control data, and generating a plurality of said second contents data by splitting said first module data according to a result of said receiving processing inputted from said arithmetic circuit via said arithmetic circuit input/output interface;
- and
- an input/output interface outputting said second contents data obtained by said splitting processing.
1 more element
The receiver comprising:
- an arithmetic circuit performing receiving processing of first module data including first contents data and first control data according to a preset program;
- an arithmetic circuit input/output interface outputting data required for said receiving processing to said arithmetic circuit, and inputting a result of said receiving processing from said arithmetic circuit;
- a receiving memory circuit storing a plurality of received second module data respectively including second contents data and second control data;
- a data reassemble/split circuit generating said first module data by reassembling a plurality of said second module data, and generating said plurality of second contents data by splitting said first module data, according to the result of said receiving processing inputted from said arithmetic circuit via said arithmetic circuit input/output interface;
- an input/output memory circuit storing said second contents data obtained by said splitting processing;
- and
- an input/output interface outputting said second contents data read from said input/output memory circuit.
4 more elements
A transmitting method for utilizing a data processing circuit and an arithmetic circuit, wherein:
- said data processing circuit generates first module data including first contents data;
- said data processing circuit outputs data required for transmitting processing of said first module data to said arithmetic circuit;
- said arithmetic circuit, operating according to a preset program, performs said transmitting processing using said data inputted and generates first control data in response to a result of said transmitting processing of said first contents data;
- said data processing circuit generates second control data based on said first control data, generates a plurality of second contents data by splitting said first module data, and generates a plurality of second module data respectively including said second contents data and said second control data;
- and
- said data processing circuit transmits said second module data.
3 more elements
A receiving method for utilizing a data processing circuit and an arithmetic circuit to perform receiving processing of first module data including first contents data and first control data:
- wherein said data processing circuit generates said first module data by reassembling a plurality of received second module data that respectively include second contents data and second control data;
- said data processing circuit outputs data required for said receiving processing of said first module data to said arithmetic circuit;
- said arithmetic circuit performs said receiving processing using data inputted from said data processing circuit;
- said data processing circuit inputs a result of said receiving processing from said arithmetic circuit;
- said data processing circuit generates a plurality of said second contents data by splitting said first module data according to a result of said receiving processing, and
- said data processing circuit outputs externally said second contents data obtained by said splitting processing.
3 more elements
Dependencies are inferred from the claim text.