Highly linear power amplifier and radio applications thereof

A linear transmitter comprises:

• processing module;
• memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to:
• determine an output power level of an outbound radio frequency (RF) signal;
• and
• enable at least one of a first enable signal and a second enable signal based on the determined output power level;
• up-conversion module operably coupled to produce an RF signal from an I component of a low intermediate frequency (IF) outbound signal, a Q component of the low IF outbound signal, an I component of a local oscillation, and a Q component of the local oscillation;
• highly linear power amplifier operably coupled to produce an amplified RF signal by amplifying the RF signal based on at least one of:
• a first enable signal and a second enable signal, wherein the highly linear power amplifier includes:
• component;
• first transistor pair coupled in series with the component, wherein a first transistor of the first transistor pair is coupled to receive the RF signal and wherein a second transistor of the first transistor pair is coupled to receive the first enable signal;
• and
• second transistor pair coupled in series with the component, wherein a first transistor of the second transistor pair is coupled to receive the RF signal, wherein a second transistor of the second transistor pair is coupled to receive the second enable signal, wherein when the first enable signal is enabled the highly linear power amplifier has a first gain with a first linearity and when the second enable signal is enabled the highly linear power amplifier has a second gain with the first linearity;
• and
• output power amplifier operably coupled to produce the outbound RF signal by further amplifying the amplified RF signal.

A radio comprising:

• receiver operably coupled to convert an inbound RF signal into an I component of an inbound low intermediate frequency (IF) signal and a Q component of the low IF signal based on an I component of a receiver local oscillation and a Q component of the receiver local oscillation;
• and
• transmitter that includes:
• processing module;
• memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to:
• determine an output power level of an outbound radio frequency (RF) signal;
• and
• enable at least one of a first enable signal and a second enable signal based on the determined output power level;
• up-conversion module operably coupled to produce an RF signal from an I component of a low intermediate frequency (IF) outbound signal, a Q component of the low IF outbound signal, an I component of a local oscillation, and a Q component of the local oscillation;
• highly linear power amplifier operably coupled to produce an amplified RF signal by amplifying the RF signal based on at least one of:
• a first enable signal and a second enable signal, wherein the highly linear power amplifier includes:
• component;
• first transistor pair coupled in series with the component, wherein a first transistor of the first transistor pair is coupled to receive the RF signal and wherein a second transistor of the first transistor pair is coupled to receive the first enable signal;
• and
• second transistor pair coupled in series with the component, wherein a first transistor of the second transistor pair is coupled to receive the RF signal, wherein a second transistor of the second transistor pair is coupled to receive the second enable signal, wherein when the first enable signal is enabled the highly linear power amplifier has a first gain with a first linearity and when the second enable signal is enabled the highly linear power amplifier has a second gain with the first linearity;
• and
• output power amplifier operably coupled to produce the outbound RF signal by further amplifying the amplified RF signal.

A differential highly linear power amplifier comprises:

• first component;
• second component;
• first differential enable transistor pair operably coupled to the first and second components, wherein the first differential enable transistor pair is operably coupled to receive a first enable signal;
• first differential input transistor pair operably coupled to the first differential enable transistor pair, wherein the first differential input transistor pair is operably coupled to receive a differential input signal;
• second differential enable transistor pair operably coupled to the first and second components, wherein the second differential enable transistor pair is operably coupled to receive a second enable signal;
• and
• second differential input transistor pair operably coupled to the second differential enable transistor pair, wherein the second differential input transistor pair is operably coupled to receive the differential input signal.