Vertical instruction and data processing in a network processor architecture
AssigneeBay Microsystems, Inc.
InventorsBarry Lee, Golchiro Ono, Man Dieu Trinh, Ryszard Bleszynski
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AssigneeBay Microsystems, Inc.
InventorsBarry Lee, Golchiro Ono, Man Dieu Trinh, Ryszard Bleszynski
Estimating the term…
An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i.e., the time to complete a process is known) and that it employs a pipelined “multiple instruction single date” (“MISD”) architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.
A method for processing an incoming information element belonging to a flow, the incoming information element comprising at least one information element segment, the method comprising:
A data pipelined processor to process an incoming information element belonging to a flow, comprising:
A method for updating a count of rollovers of a timer for a flow in order to accurately time stamp an incoming information element belonging to the flow, comprising:
A system for updating a count of rollovers of a timer for a flow in order to accurately time stamp an incoming information element belonging to the flow, comprising:
A method for converting a first protocol of an incoming information element having a first length to a second protocol, comprising:
A system for converting a first protocol of an incoming information element having a first length to a second protocol, comprising:
A method to maintain activity-levels of a plurality of flows, comprising:
A method to maintain activity-levels of a plurality of flows, comprising:
A method to manage storage allocation to a plurality of flows, comprising:
A system to maintain a plurality of activity-levels corresponding to a plurality of flows, comprising:
For a port, a method to create a chain associated with the port, the chain includes a plurality of information segment storage units belonging to at least one flow that is an unassigned bit rate (“UBR”) flow and assigned to the port, comprising:
A method for storing within at least one fixed-size buffer a current one of at least one information element that all have the same input logical port number and priority, wherein each one of the at least one information element includes at least one information element segment, comprising:
A system for storing within at least one fixed-size buffer a current one of at least one information element that all have the same input logical port number and priority, wherein each one of the at least one information element includes at least one information element segment, comprising:
Dependencies are inferred from the claim text.