Synchronous flash memory command sequence
AssigneeMicron Technology, Inc.
InventorsCliff Zitlaw, Frankie Fariborz Roohparvar
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Abstract
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.
Claims21
A synchronous flash memory device comprising:
- an array of non-volatile memory cells;
- and
- a command register to store command data used to control flash memory operations, wherein the command register is coupled to receive the command data through memory address connections during an internal flash operating mode, wherein the internal flash operating mode is initiated using a predetermined sequence of ACTIVE, WRITE, and/or READ commands.
The synchronous flash memory device of claim I further comprising a control circuit to perform a program operation following the initiation of the internal flash operating mode in response to an ACTIVE command and a WRITE command.
A synchronous flash memory device comprising:
- an array of non-volatile memory cells arranged in addressable blocks;
- external address connections to receive externally provided address data;
- a mode register to store mode data used to set a mode of the synchronous flash memory device;
- and
- a command register to store command data used to control flash memory operations, wherein the command register is coupled to receive the command data through memory address connections during an internal flash operating mode, wherein the internal flash operating mode is initiated using a sequence comprising ACTIVE, WRITE, and/or READ commands.
A synchronous flash memory device comprising:
- an array of non-volatile memory cells;
- and
- a control circuit to initiate a command operation in response to a predefined sequence of externally provided ACTIVE, WRITE, and/or READ commands.
A synchronous data system comprising:
- a memory controller;
- and
- a synchronous flash memory device coupled to the memory controller and comprising,
- an array of non-volatile memory cells, and
- a control circuit to initiate a command operation in response to a predefined sequence of externally provided ACTIVE, WRITE, and/or READ commands from the memory controller.
A method of loading commands in a synchronous flash memory, the method comprising:
- initiating a command register load operation using a predefined combination of ACTIVE, WRITE, and/or READ commands, wherein the ACTIVE commands are defined as a high column address strobe (CAS#) signal, a low row address strobe (RAS#) signal, and a high write enable (WE#) signal, and the WRITE commands are defined as a low column address strobe (CAS#) signal, a high row address strobe (RAS#) signal, and a low write enable (WE#) signal;
- and
- loading command information into the command register using address connections of the synchronous flash memory in response to the command register load operation.
Dependencies are inferred from the claim text.