Synchronous flash memory command sequence
AssigneeMicron Technology, Inc.
InventorsCliff Zitlaw, Frankie Fariborz Roohparvar
Life of this patent
Estimating the term…
Abstract
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.
Claims22
A synchronous data system comprising:
- a memory controller;
- and
- a synchronous flash memory device coupled to the memory controller and comprising,
- an array of non-volatile memory cells, and
- a command register to store command information used to control flash memory operations, wherein the command register is coupled to receive the command information through memory address connections during a load command register operating mode, wherein the load command register operating mode is initiated using a command sequence comprising a plurality of WRITE commands defined as a low CAS# signal, a high RAS# signal, and a low WE# signal.
A method of providing commands to a synchronous flash memory, the method comprising:
- initiating a command register load operation using a predefined command sequence comprising a plurality of WRITE commands, defined as a low column address strobe (CAS#) signal, a high row address strobe (RAS#) signal, and a low write enable (WE#) signal;
- and
- loading command information into the command register using address connections of the synchronous flash memory in response to the command register load operation.
A method of providing commands to a synchronous flash memory, the method comprising:
- initiating a command register load operation using a predefined command sequence comprising a selected sequence of ACTIVE, WRITE, and/or READ commands;
- and
- loading command information into the command register using address connections of the synchronous flash memory in response to the command register load operation.
Dependencies are inferred from the claim text.