Dram power-source controller

A DRAM power-source controller of comprising power-source-voltage control means for supplying the voltage of an external power source as that of an internal power source when detecting the enable stage of the RAM and setting the internal power source to the ground level when detecting the disable state of the DRAM.

A DRAM power-source controller comprising:

• power-source-voltage control means for supplying the voltage of an external power source as that of an internal power source when detecting the enable state of the DRAM and supplying a voltage lower than that of the external power source to the internal power source when detecting the disable state of the DRAM, wherein
• the power-source-voltage control means is constituted by an internal-power-source driver circuit having a switching device, a mode detection circuit for outputting an L-level signal when detecting the enable state of the DRAM through a predetermined input terminal and inverting the signal into H-level when detecting the disable state of the DRAM through the input terminal, and an internal-power-source reference circuit for controlling the switching device of the internal-power-source driver circuit so that an internal power source has a voltage equal to the voltage of an external power source when a signal output from the mode detection circuit is kept L-level and controlling the switching device of the internal-power-source driver circuit so that the internal power source has a voltage lower than that of the external power source when the signal output from the mode detection circuit is inverted into H-level.

A DRAM-power-source controller comprising power-source-voltage control means for supplying the voltage of an external power source as that of an internal power source when detecting the enable state of the DRAM and setting the internal power source to the ground level when detecting the disable state of the DRAM, wherein

• the power-source-voltage control means is constituted by an internal-power-source driver circuit having a switching device, a mode detection circuit for outputting an L-level signal when detecting the enable state of the DRAM through a predetermined input terminal and inverting the signal into H-level when detecting the disable state of the DRAM through the input terminal, and an driver control circuit for controlling the switching device of the internal-power-source driver circuit so that an internal power source has a voltage equal to the voltage of an external power source when a signal output from the mode detection circuit is kept L-level and controlling the switching device of the internal-power-source driver circuit so that the internal power source is set to the ground level when the signal output from the mode detection circuit is inverted into H-level.