High speed DRAM architecture with uniform access latency
AssigneeMosaid Technologies Incorporated
InventorPaul Demone
Life of this patent
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Abstract
A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
Claims11
A Dynamic Random Access Memory (DRAM) for performing read, write, and refresh operations, said DRAM comprising:
- (a) a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line;
- (b) a word line enable device for asserting a selected one of said word lines;
- (c) a column select device for asserting a selected one of said bit line pairs;
- (d) a timing circuit for controlling said word line enable device, said column select device, and said read, write, and refresh operations in response to a word line timing pulse, wherein said read, write, and refresh operation are performed in the same amount of time.
A memory device for storing data in address locations specified input addresses, said memory device responsive only to read, write and refresh commands, each of said commands having a uniform latency independent of said input addresses.
A method for performing a read command in a memory device in synchronization with a system clock comprising the steps of:
- (a) generating a main self-timed pulse derived from the system clock;
- and
- (b) generating a plurality of self-timed pulses activated in cascade based on said main self-timed pulse for controlling operation of address and data circuits.
Dependencies are inferred from the claim text.