Method and apparatus for supplementary command bus
AssigneeMicron Technology, Inc.
InventorPaul A. LaBerge
Life of this patent
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Abstract
An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured to transfer address-specific commands and a supplementary command bus configured to transfer general commands. Commands may be received by the memory simultaneously at the respective interfaces.
Claims21
An electronic system, comprising:
- a processor;
- a memory having more than one memory location;
- and
- a bus connecting the processor to the memory, wherein the bus comprises:
- a data bus for transmitting data;
- an address bus for identifying a first memory location;
- a main command bus for transferring a first command that relates to the first memory location;
- and
- a supplementary command bus for transferring a second command, wherein the second command does not relate to the first memory location.
An electronic system, comprising:
- a processor;
- a memory having more than one memory location;
- and
- a bus connecting the processor to the memory, wherein the bus comprises:
- a main command bus configured to transfer an address-specific command;
- and
- a supplementary command bus configured to transfer a general command.
A memory having an interface, wherein the interface comprises:
- a location-specific command interface configured to receive location-specific commands;
- and
- a general command interface configured to receive only one or more general commands.
A memory having an interface, wherein the interface comprises a general command interface configured to receive a general command.
A memory including a one-bit PRECHARGE input dedicated to receiving a PRECHARGE command.
A memory system, comprising:
- a memory controller;
- and
- a memory in communication with the memory controller, wherein the memory includes an interface, comprising:
- a main control interface for receiving a location-specific command;
- and
- a supplementary control interface for receiving a general command.
An electronic system, comprising:
- a processor;
- and
- a memory system connected to the processor, comprising:
- a memory controller connected to the processor;
- and
- a memory connected to the memory controller and having an interface, comprising:
- an address interface for receiving an address signal;
- a main control interface, comprising:
- a main command bus for receiving a first command signal relating to a memory location specified by the address signal;
- and
- a main bank select bus for receiving a first bank select signal specifying a first bank corresponding to the first command signal;
- and
- a supplementary control interface, comprising:
- a supplementary command bus for receiving a second command signal, wherein the second command signal corresponds to a general command;
- and
- a supplementary bank select bus for receiving a second bank signal specifying a second bank corresponding to the second command signal.
A method of accessing a memory, comprising:
- in a first time slot, requesting activation of a first row;
- in a second time slot, requesting an access of a memory location in the first row;
- in a third time slot, requesting activation of a second row and requesting closure the first row.
Dependencies are inferred from the claim text.