Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation

A voltage switching circuit for supplying a reference voltage to a charge pump, the voltage switching circuit comprising:

• an active voltage reference adapted to receive a mode signal, the active voltage reference operable responsive to the mode signal going active to generate a first reference voltage and operable responsive to the mode signal going inactive to terminate generation of the first reference voltage;
• a standby voltage reference operable to generate a second reference voltage;
• a charge pump operable to generate a row drive voltage having a value that is a function of a reference voltage;
• a plurality of row drivers, each row driver being adapted to receive a corresponding address signal and including a word line output, and being coupled to the charge pump to receive the row drive voltage, the row driver applying the row drive voltage on the word line output responsive to the address signal being active;
• a multiplexer coupled to the active and standby voltage references to receive the first and second voltage references, respectively, and being coupled to the charge pump, the multiplexer applying the first reference voltage to the charge pump responsive to a selection signal going active, and applying the second reference voltage to the charge pump responsive to the selection signal going inactive;
• a delay circuit coupled to the multiplexer and adapted to receive the mode signal, the delay circuit operable responsive to the mode signal going active to drive the selection signal active a delay time after the mode signal goes active, and operable responsive to the mode signal going inactive to drive the selection signal inactive without the delay time.

A voltage switching circuit, comprising:

• a switch having a first terminal adapted to receive a supply voltage, a second terminal, and a control terminal adapted to receive a mode signal;
• an active voltage reference coupled to the second terminal of the switch and including an output;
• a standby voltage reference including an output;
• a multiplexer having an output, a first input coupled to the output of the active voltage reference and a second input coupled to the output of the standby voltage reference, and having a selection input;
• and
• a delay circuit coupled to the selection input of the multiplexer and having an input adapted to receive the mode signal.

A voltage switching circuit, comprising:

• a first voltage generating means adapted to receive a mode signal for generating a first reference voltage responsive to the mode signal going active and for terminating generation of the first reference voltage responsive to the mode signal going inactive;
• a second voltage generating means for generating a second reference voltage;
• a selection means coupled to the first and second voltage reference means for outputting the first reference voltage on an output responsive to a selection signal going active and for outputting the second reference voltage on the output responsive to the selection signal going inactive;
• and
• a delay means coupled to the selection means and adapted to receive the mode signal for activating the selection signal a delay time after the mode signal goes active and for deactivating the selection signal responsive to the mode signal going inactive.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array including a plurality of word lines;
• a voltage switching circuit, comprising,
• an active voltage reference adapted to receive a mode signal, the active voltage reference operable responsive to the mode signal going active to generate a first reference voltage and operable responsive to the mode signal going inactive to terminate generation of the first reference voltage;
• a standby voltage reference operable to generate a second reference voltage;
• a charge pump operable to generate a row drive voltage having a value that is a function of a reference voltage;
• a plurality of row drivers, each row driver being coupled to the address decoder to receive a corresponding decoded address signal and including an output coupled to a corresponding word line of the memory-cell array, and coupled to the charge pump to receive the row drive voltage, the row driver applying the row drive voltage on the word line responsive to the decoded address signal being active;
• a multiplexer coupled to the active and standby voltage references to receive the first and second voltage references, respectively, and being coupled to the charge pump, the multiplexer applying the first reference voltage to the charge pump responsive to a selection signal going active, and applying the second reference voltage to the charge pump responsive to the selection signal going inactive;
• a delay circuit coupled to the multiplexer and adapted to receive the mode signal, the delay circuit operable responsive to the mode signal going active to drive the selection signal active a delay time after the mode signal goes active, and operable responsive to the mode signal going inactive to drive the selection signal inactive without the delay time.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, the memory device comprising,
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array including a plurality of word lines;
• a voltage switching circuit, comprising,
• an active voltage reference adapted to receive a mode signal, the active voltage reference operable responsive to the mode signal going active to generate a first reference voltage and operable responsive to the mode signal going inactive to terminate generation of the first reference voltage;
• a standby voltage reference operable to generate a second reference voltage;
• a charge pump operable to generate a row drive voltage having a value that is a function of a reference voltage;
• a plurality of row drivers, each row driver being coupled to the address decoder to receive a corresponding decoded address signal and including an output coupled to a corresponding word line of the memory-cell array, and coupled to the charge pump to receive the row drive voltage, the row driver applying the row drive voltage on the word line responsive to the decoded address signal being active;
• a multiplexer coupled to the active and standby voltage references to receive the first and second voltage references, respectively, and being coupled to the charge pump, the multiplexer applying the first reference voltage to the charge pump responsive to a selection signal going active, and applying the second reference voltage to the charge pump responsive to the selection signal going inactive;
• a delay circuit coupled to the multiplexer and adapted to receive the mode signal, the delay circuit operable responsive to the mode signal going active to drive the selection signal active a delay time after the mode signal goes active, and operable responsive to the mode signal going inactive to drive the selection signal inactive without the delay time.

A method of operating a memory, the method comprising:

• detecting an active mode of operation of the memory;
• during the active mode of operation, generating a first reference voltage;
• generating a word line drive voltage using the first reference voltage;
• receiving addresses corresponding to memory cells to be accessed;
• and
• applying the word line drive voltage to the word line of addressed memory cells to access the memory cells in the corresponding row;
• and
• detecting a standby mode of operation;
• and
• during the standby mode of operation,
• terminating generation of the first reference voltage;
• generating a second reference voltage;
• and
• generating the word line drive voltage using the second reference voltage.

A method of operating a memory, the method comprising:

• detecting an active mode of operation of the memory;
• during the active mode of operation,
• generating a first reference voltage that consumes a first amount of power in generating the first reference voltage;
• generating a word line drive voltage using the first reference voltage;
• generating a second reference voltage that consumes a second amount of power in generating the second reference voltage, the second amount of power being less than the first amount of power;
• detecting a standby mode of operation of the memory;
• and
• during the standby mode,
• terminating generation of the first reference voltage;
• and
• generating the word line drive voltage using the second reference voltage.

A method of operating a memory, the method comprising:

• detecting a standby mode of operation of the memory;
• generating a first reference voltage;
• generating a word line drive voltage using the first reference voltage;
• detecting an active mode of operation of the memory;
• during the active mode of operation,
• generating a second reference voltage;
• generating the word line drive voltage using the first reference voltage;
• and
• generating the word line drive voltage using the second reference voltage.

A method of operating a memory, the method comprising:

• generating a first reference voltage;
• detecting an active mode of operation of the memory;
• upon detection of the active mode,
• commencing the charging of a node to develop a second reference voltage on the node, the second reference voltage having desired value;
• generating the word line drive voltage using the first reference voltage while the node is charging the second reference voltage to the desired value;
• and
• generating the word line drive voltage using the second reference voltage once the second reference voltage on the node has been charged to the desired value;
• detecting a standby mode of operation of the memory;
• upon detection of the standby mode,
• terminating the charging of the node;
• and
• generating the word line drive voltage using the first reference voltage.