SRAM array with temperature-compensated threshold voltage

A method of providing a temperature-compensated pull-down threshold voltage VT, comprising:

• comparing a controlled temperature-based voltage reference to a VT-dependent voltage, including:
• providing a comparator having a first input, a second input and an output;
• receiving the VT-dependent voltage at the first input of the comparator;
• receiving the controlled temperature-based voltage reference at the second input of the comparator;
• and
• providing a control signal indicative based on the comparison between the controlled temperature-based voltage reference to the VT-dependent voltage;
• and
• generating a temperature-compensated bias voltage for a transistor body terminal based on the comparison between the temperature-based voltage reference and the VT-dependent voltage, including:
• providing a charge pump to receive the control signal and coupling the charge pump to a number of transistor body terminals;
• and
• in response to receiving the control signal at the charge pump, using the charge pump to charge the number of transistor body terminals.

A method of providing a temperature-compensated pull-down threshold voltage VT for at least one transistor, comprising:

• providing at least one triple-well transistor, wherein each triple-well transistor includes:
• a p-substrate;
• a p-well isolated from the p-substrate by an n-tub electrically coupled to an n-well;
• an NMOS transistor formed within the isolated p-well;
• an n+ contact for the n-well;
• and
• a VBB p+ contact for the p-well, wherein the VBB p+ contact functions as a body terminal;
• determining whether a VT-dependent voltage is less than a first reference voltage that corresponds to a VTmin or more than a second reference voltage that corresponds to a VTmax;
• and
• in response to determining that the VT-dependent voltage is less than the first reference voltage that corresponds to the VTmin, charging the transistor body terminal of each of the plurality of triple-well transistors until the VT-dependent voltage is more than the second reference voltage that corresponds to the VTmax.

A method of providing a temperature-compensated pull-down threshold voltage VT for a memory array, comprising:

• providing an LL4TCMOS SRAM array that includes a plurality of transistors with a body terminal and a threshold voltage VT;
• determining whether a VT-dependent voltage is less than a first reference voltage that corresponds to a VTmin or more than a second reference voltage that corresponds to a VTmax;
• and
• in response to determining that the VT-dependent voltage is less than the first reference voltage that corresponds to the VTmin, charging the transistor body terminal of each of the plurality of transistors until the VT-dependent voltage is more than the second reference voltage that corresponds to the VTmax.

A method of providing a temperature-compensated pull-down threshold voltage VT for a memory array, comprising:

• providing an LL4TCMOS SRAM array that includes a plurality of triple-well transistors, wherein each triple-well transistor includes:
• a p-substrate;
• a p-well isolated from the p-substrate by an n-tub electrically coupled to an n-well;
• an NMOS transistor formed within the isolated p-well;
• an n+ contact for the n-well;
• and
• a VBB P+ contact for the p-well, wherein the VBB p+ contact functions as a body terminal;
• determining whether a VT-dependent voltage is less than a first reference voltage that corresponds to a VTmin or more than a second reference voltage that corresponds to a VTmax;
• and
• in response to determining that the VT-dependent voltage is less than the first reference voltage that corresponds to the VTmin, charging the transistor body terminal of each of the plurality of triple-well transistors until the VT-dependent voltage is more than the second reference voltage that corresponds to the VTmax.

A method of providing a temperature-compensated pull-down threshold voltage VT for a memory array, comprising:

• providing a comparator having a first input, a second input, and an output;
• providing a charge pump;
• coupling the charge pump to the comparator and to a body terminal of each pull-down transistor contained within an array of pull-down transistors in the memory array;
• receiving a VT-dependent voltage at the first input of the comparator;
• receiving a reference voltage with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage) at the second input of the comparator;
• providing a control signal to the charge pump, wherein the control signal is indicative of whether the VT-dependent voltage is less than a first reference voltage or more than a second reference voltage;
• in response to receiving a control signal indicating that the VT-dependent voltage is less than the first reference voltage, charging the body terminal of each pull-down transistor contained within an array of pull-down transistors in the memory array;
• and
• in response to receiving a control signal indicating that the VT-dependent voltage is more than the second reference voltage, ceasing to charge the body terminal of each pull-down transistor contained within an array of pull-down transistors in the memory array.

A method of forming a transistor body bias generator, comprising:

• providing a charge pump with an output adapted to couple to a body terminal of at least one transistor;
• providing a comparator with a first input, a second input and an output;
• coupling the first input to a reference voltage with reduced temperature dependence with positive or negative slope (RTDWPNS reference voltage);
• coupling the second input to a VT-dependent voltage;
• and
• coupling the output to the charge pump to present a control signal to the charge pump, wherein the charge pump is adapted to compensate for temperature changes by selectively charging the body terminal of the at least one transistor in response to the control signal.

A method of forming a memory array, comprising:

• providing a plurality of triple-well transistors having a body terminal and a threshold voltage VT;
• providing a comparator having a first input, a second input, and an output;
• providing a charge pump;
• coupling the charge pump to the body terminal of each of the plurality of triple-well transistors;
• coupling a VT-dependent voltage at the first input of the comparator;
• coupling a reference voltage at the second input of the comparator;
• and
• coupling the output of the comparator to the charge pump such that the charge pump is controlled by a control signal based on a comparison between the VT-dependent voltage and the reference voltage.

A method of forming a memory array, comprising:

• providing a bank of transistors having a body terminal and a threshold voltage VT;
• providing a memory array, including providing a plurality of transistors having a body terminal;
• providing a comparator having a first input, a second input, and an output;
• providing a charge pump;
• coupling the charge pump to the body terminal for the bank of transistors and to the body terminal of each of the plurality of transistors in the memory array;
• coupling a VT-dependent voltage from the bank of transistors to the first input of the comparator;
• coupling a reference voltage at the second input of the comparator;
• and
• coupling the output of the comparator to the charge pump such that the charge pump is controlled by a control signal based on a comparison between the VT-dependent voltage and the reference voltage.

A method-of forming a memory array, comprising:

• providing a bank of transistors having a body terminal and a threshold voltage VT;
• providing a LL4TCMOS SRAM array, including providing a plurality of transistors having a body terminal;
• providing a comparator having a first input, a second input, and an output;
• providing a charge pump;
• coupling the charge pump to the body terminal for the bank of transistors and to the body terminal of each of the plurality of transistors in the LL4TCMOS SRAM array;
• coupling a VT-dependent voltage from the bank of transistors to the first input of the comparator;
• coupling a reference voltage at the second input of the comparator;
• and
• coupling the output of the comparator to the charge pump such that the charge pump is controlled by a control signal based on a comparison between the VT-dependent voltage and the reference voltage.

A method of forming a memory array, comprising:

• providing a bank of triple-well transistors having a body terminal and a threshold voltage VT;
• providing a LL4TCMOS SRAM array, including providing a plurality of triple-well transistors having a body terminal;
• providing a comparator having a first input, a second input, and an output;
• providing a charge pump;
• coupling the charge pump to the body terminal for the bank of triple-well transistors and to the body terminal of each of the plurality of triple-well transistors in the LL4TCMOS SRAM array;
• coupling a VT-dependent voltage from the bank of triple-well transistors to the first input of the comparator;
• coupling a reference voltage at the second input of the comparator;
• and
• coupling the output of the comparator to the charge pump such that the charge pump is controlled by a control signal based on a comparison between the VT-dependent voltage and the reference voltage.