Semiconductor memory device including page latch circuit
AssigneeKabushiki Kaisha Toshiba
InventorsJunichiro Noda, Tamio Ikehashi, Kenichi Imamiya
Life of this patent
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Abstract
A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.
Claims41
A semiconductor memory device having a data latch circuit, the semiconductor memory device comprising:
- a plurality of bit lines to which a reprogrammable memory cell is connected;
- a data bus on which data is transferred;
- a latch connected to each of the plurality of bit lines;
- a read out circuit connected to the data bus;
- and
- a data transfer circuit group having an ability to directly transfer the data loaded in the latch circuit, to the read out circuit without being transferred to the memory cell.
A semiconductor memory device having a data latch circuit, the semiconductor memory device comprising:
- a plurality of bit lines to which a reprogrammable memory cell is connected;
- a data bus on which data is transferred;
- a latch circuit configured to latch the data transferred on the data bus;
- a read out circuit connected to the data bus;
- and
- a data transfer circuit group;
- wherein the data transfer circuit group is controlled so as to transfer the data latched in the latch circuit to the read out circuit without being transferred to the memory cell.
A test method of a semiconductor memory device, the method comprising:
- latching data in a page latch via a data bus on which the data are transferred;
- and
- transferring the data latched in the page latch to a cell matrix for storing the data in a first mode and to a read-out circuit in a second mode for testing whether or not an error occurs in a data transfer circuit group including the data bus, the page latch and read out circuit.
Dependencies are inferred from the claim text.