Input/output buffer circuit
AssigneeOki Electric Industry Co., Ltd.
InventorToshihide Nagatome
Life of this patent
Estimating the term…
Abstract
An input/output buffer circuit is capable of suppressing an increase in current consumption of the whole system even in a low power consumption mode for bringing a clock to a halt. The input/output buffer circuit has an input/output terminal (10) for performing the input/output of data. When a write enable signal WR is in an active state, the input/output buffer circuit outputs a signal to the input/output terminal (10). When a read enable signal RD is in an active state, the input/output buffer circuit receives data from the input/output terminal (10). When the write enable signal RD and the read enable signal WR are both in a non-active state, the input/output buffer circuit outputs a signal based on any of signals supplied thereto.
Claims18
An input/output buffer circuit comprising:
- an input/output terminal for performing the input/output of data;
- said input/output buffer circuit outputting a signal to the input/output terminal when a write enable signal is in an active state, and receiving data from the input/output terminal when a read enable signal is in an active state,
- wherein when the write enable signal and the read enable signal are both in a non-active state, a signal based on any of signals supplied to the input/output buffer circuit is outputted.
An input/output buffer circuit comprising:
- an input/output terminal for receiving an input signal and for outputting an output signal;
- an input circuit connected to the input/output terminal, the input circuit transferring the input signal when a read enable signal is in an active state, the input circuit outputting a predetermined signal when the read enable signal is in an inactive state;
- and
- an output circuit connected to the input/output terminal, the output circuit outputting the output signal when a write enable signal is in the active state, the output circuit outputting a predetermined signal when the read enable signal and the write enable signal are in the inactive state, the output circuit outputting high impedance signal when the write enable signal is in the inactive state and the read enable signal is in the active state.
An input/output buffer circuit comprising:
- an input/output terminal for receiving an input signal and for outputting an output signal;
- an input circuit connected to the input/output terminal, the input circuit transferring the input signal;
- and
- an output circuit connected to the input/output terminal, the output circuit outputting the output signal when a write enable signal is in the active state, the output circuit outputting a predetermined signal when a read enable signal and the write enable signal are in an inactive state, the output circuit outputting high impedance signal when the write enable signal is in the inactive state and the read enable signal is in an active state.
Dependencies are inferred from the claim text.