Regulation method for the drain, body and source terminals voltages in a non-volatile memory cell during a program phase and corresponding program circuit
AssigneeSTMicroelectronics S.r.I.
InventorsRino Micheloni, Sabina Mognoni, Ilaria Motta, Andrea Sacco
Life of this patent
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Abstract
A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.
Claims7
A method of regulating the voltages at the drain and body source terminals (D,S) of a non-volatile memory cell (3) being programmed, wherein said voltages are applied through a program circuit (1) connected in a conduction pattern for transferring a predetermined voltage value (VPD,Vb) to at least one terminal (D,B) of the memory cell;
- characterized in that it comprises a step of regulating said voltage value locally within said program-load circuit to void the effect of a parasitic resistor Rpar) present in said pattern.
A program-load circuit (1) incorporated in a semiconductor-integrated electronic memory device (2) including a non-volatile memory cell array (3), wherein each cell comprises at least one floating gate transistor having source, drain, gate and body terminals (S,D,G,B), each program-load circuit (1) being connected in a conduction pattern for transferring a predetermined voltage value (VPD,Vb) to a terminal (D,B) of the memory cell;
- characterized in that it includes a stage (5) for regulating said voltage locally and voiding the effect of a parasitic resistor (Rpar) present in said pattern.
Dependencies are inferred from the claim text.