System, method, and apparatus for multi-level hierarchical Z buffering

A data processing apparatus, said apparatus comprising:

• a combining cache configured to store a first plurality of first-level representative Z values;
• a primary representative Z value memory configured to store first-level representative Z values;
• and
• a logic circuit configured to receive the first plurality of first-level representative Z values, to receive a corresponding second plurality of first-level representative Z values from the primary representative Z value memory, and to compare the first plurality of first-level representative Z values with the second plurality of first-level representative Z values,
• wherein said logic circuit is configured to determine a second-level representative Z value from the first plurality of first-level representative Z values.

A data storage medium having machine-readable code stored thereon, the machine-readable code comprising instructions executable by an array of logic elements, the instructions defining a method of signal reception, said method comprising:

• receiving a plurality of first-level representative Z values, each representing a block of Z values;
• determining a second-level representative Z value from the plurality of first-level representative Z values;
• updating a primary representative Z value memory based on the plurality of received first-level representative Z values;
• and
• comparing a fragment Z value with the second-level representative Z value.