Driver circuit for liquid crystal display panel

A selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprising:

• a gray level reference voltage generating section which generates said 2N gray level reference voltages;
• a plurality of common reference voltage lines which, by means of time division, are serially supplied with M gray level reference voltages of said 2N gray level reference voltages;
• a plurality of select transistor arrays which are provided in parallel between said plurality of common reference voltage lines and an output terminal, and each of which has a plurality of serially connected transistors that are controlled in accordance with said input data;
• a voltage holding circuit for holding voltages supplied to said output terminal;
• and
• a time division control circuit which causes said select transistor arrays to assume a drive enabled state in correspondence with a gray level reference voltage which is selected, in accordance with said input data, from among said group of M gray level reference voltages, and then controls the select transistor arrays to be non-conductive and causes said voltage holding circuit to hold the selected gray level reference voltage.

A selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprising:

• a gray level reference voltage generating section which generates said 2N gray level reference voltages;
• a plurality of common reference voltage lines which, by means of time division, are serially supplied with adjacent first and second gray level reference voltages of said 2N gray level reference voltages;
• a plurality of select transistor arrays which are provided in parallel between said plurality of common reference voltage lines and an output terminal, and each of which has a plurality of serially connected transistors that are controlled in accordance with said input data;
• a voltage holding circuit for holding voltages supplied to said output terminal;
• and
• a time division control circuit which, in a first drive period, causes said plurality of select transistor arrays to assume a drive enabled state to thereby cause one of said first and second gray level reference voltages to be outputted to said output terminal via a select transistor array selected in accordance with said input data, and, in a second drive period following said first drive period, causes said plurality of select transistor arrays to assume a drive enabled state or a drive disabled state in accordance with a prescribed bit signal of said input data, and, during a drive enabled state, causes the other of the first and second gray level reference voltages to be outputted to said output terminal via said selected select transistor array.

A liquid crystal display panel driver circuit, comprising:

• a selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, said selector circuit including:
• a gray level reference voltage generating section which generates said 2N gray level reference voltages;
• a plurality of select transistor arrays which are provided in parallel between terminals of said gray level reference voltages and an output terminal and each of which has a plurality of serially connected transistors that are drive-controlled in accordance with said input data, each of said select transistor arrays being commonly provided for a group of M (M is a plurality and M<2N) gray level reference voltages among the 2N gray level reference voltages;
• and
• a time division control circuit which causes said select transistor arrays to assume a drive enabled state by means of time division in correspondence with said M gray level reference voltages.

A liquid crystal display panel driver circuit, comprising:

• a selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, said selector circuit including:
• a gray level reference voltage generating section which generates said 2N gray level reference voltages;
• a plurality of common reference voltage lines which, by means of time division, are serially supplied with M gray level reference voltages of said 2N gray level reference voltages;
• a plurality of select transistor arrays which are provided in parallel between said plurality of common reference voltage lines and an output terminal, and each of which has a plurality of serially connected transistors that are controlled in accordance with said input data;
• a voltage holding circuit for holding voltages supplied to said output terminal;
• and
• a time division control circuit which causes said select transistor arrays to assume a drive enabled state in correspondence with a gray level reference voltage which is selected, in accordance with said input data, from among said group of M gray level reference voltages, and then controls the select transistor arrays to be non-conductive and causes said voltage holding circuit to hold the selected gray level reference voltage.

A liquid crystal display panel driver circuit, comprising:

• a selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprising:
• a gray level reference voltage generating section which generates said 2N gray level reference voltages;
• a plurality of common reference voltage lines which, by means of time division, are serially supplied with adjacent first and second gray level reference voltages of said 2N gray level reference voltages;
• a plurality of select transistor arrays which are provided in parallel between said plurality of common reference voltage lines and an output terminal, and each of which has a plurality of serially connected transistors that are controlled in accordance with said input data;
• a voltage holding circuit for holding voltages supplied to said output terminal;
• and
• a time division control circuit which, in a first drive period, causes said plurality of select transistor arrays to assume a drive enabled state to thereby cause one of said first and second gray level reference voltages to be outputted to said output terminal via a select transistor array selected in accordance with said input data, and, in a second drive period following said first drive period, causes said plurality of select transistor arrays to assume a drive enabled state or a drive disabled state in accordance with a prescribed bit signal of said input data, and, during a drive enabled state, causes the other of the first and second gray level reference voltages to be outputted to said output terminal via said selected select transistor array.