Data-directed scrambler for noise-shaping mixed-signal converters with an arbitrary number of quantization levels

A digital-to-analog converter comprising:

• a code converter for converting a digital input to N equally-weighted digital signals, where N is not an integer power of 2;
• a rotator for rotating the N equally-weighted digital signals in a sequence of rotator states in respective clock cycles to provide N rotated digital signals;
• a data-directed scrambler having N inputs and N outputs for data-directed scrambling of the rotated digital signals to distribute the N equally-weighted digital signals to each of the N outputs of said scrambler such that the usage of the N outputs is dynamically balanced over a relatively small number of clock cycles;
• a digital-to-analog converter circuit including N equally-weighted digital-to-analog converter elements for converting the scrambled digital signals to analog outputs;
• and
• a summing circuit for summing the outputs of the digital-to-analog converter elements to produce an analog output that represents the digital input.

An analog-to-digital converter comprising:

• a summing unit for subtracting a feedback signal from an analog input signal and providing a summing unit output;
• a loop filter for receiving said summing unit output and providing a filter output signal;
• a multi-bit quantizer for providing a digital output in response to said filter output signal;
• and
• a digital-to-analog converter responsive to said digital output for providing said feedback signal to said summing unit, said digital-to-analog converter comprising:
• an encoder for converting said digital output to N equally-weighted digital signals, where N is not an integer power of 2;
• a rotator for rotating the N equally-weighted digital signals in a sequence of rotator states in respective clock cycles to provide N rotated digital signals;
• a data-directed scrambler having N inputs and N outputs for data-directed scrambling of the rotated digital signals to distribute the N equally-weighted digital signals to each of the N outputs of said scrambler such that the usage of the N outputs is dynamically balanced over a relatively small number of clock cycles;
• a digital-to-analog converter circuit for converting the scrambled digital signals to respective analog values;
• and
• a summing circuit for summing said analog values to produce said feedback signal, wherein the digital output of said multi-bit quantizer represents the analog input signal.