Phase comparator
AssigneeNEC Electronics Corporation
InventorsTomonari Aoki, Kazuhiro Nakajima
Life of this patent
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Abstract
A phase comparator is disclosed that can provide a phase comparison result at high speed that essentially does not vary according a power source voltage, ambient temperature and/or manufacturing process conditions, or the like. A phase comparator (10) may include one-shot pulse generating units (14 and 24) that output one-shot pulses according to input data signal DAT and clock signal CLK, respectively. An R-S flip-flop (16) can receive one-shot pulses from one-shot pulse generating units (14 and 24) at set and reset inputs, respectively. An output flip-flop (17) can select between an output signal of R-S flip-flop (16) and a delay signal “a8” generated from input data signal DAT, and latch such a result according to a delayed clocks signal CLK.
Claims20
A phase comparator for determining a phase lead or phase lag between phases of a first pulse signal and a second pulse signal, comprising:
- a reset-set (R-S) flip-flop that is set or reset in accordance with a phase difference between the first pulse signal and the second pulse signal;
- and
- a D-type flip-flop that latches an output from the R-S flip-flop according to a clock input, the clock input being a delay pulse signal obtained by delaying the second pulse signal.
A phase comparator circuit, comprising, comprising:
- a first pulse generating circuit for generating first pulses corresponding to a first signal phase of a first signal;
- a second pulse generating circuit for generating second pulses corresponding to a second signal phase of a second signal;
- a pulse receiving circuit that provides a detect output that has a first value in response to a first pulse and a second value in response to a second pulse;
- and
- an output circuit for logically combining the detect output with a delayed second signal.
A phase comparator, comprising:
- a pulse input circuit that provides a first output value in response to pulses generated from a first signal and a second output value in response to pulses generated from a second signal;
- and
- an output circuit that includes at least one input gate that outputs either a delayed first signal or a logical combination of the delayed first signal and the output value from the pulse input circuit.
Dependencies are inferred from the claim text.