US 2003/0151455 A1 · Circuit for detecting and correcting central level of FSK demodulation signal

Abstract

A circuit for detecting and correcting a central level according to the present invention is constituted such that there occurs a case that the length of a code of “1” or “0” in an FSK signal extremely long, and even if this extremely long code superimposed with a frequency fluctuation of a transmitter/receiver is received, a central level can always be detected accurately. This circuit is provided with sample value holding circuits exclusive to “1” and “0” of an input demodulation data signal respectively. After a difference voltage between both sample values is once converted to a digital code in an ADA converter, and the converted code is re-converted to an analog value, thereby holding the value digitally. When “1”s continue sequentially, the hold voltage to “1” is momently updated to new values and simultaneously a voltage obtained by subtracting the difference voltage from the above-described voltage is applied to the holding circuit for “0” to update the value in the holding circuit. Also, when “0”s continue sequentially, the processing proceeds in reverse to the former case and simultaneously with a self-updating the holding circuit for “1” is updated with a voltage obtained by adding the difference voltage to the hold voltage so that a determination on data information is made as a reference value for a comparator CMP utilizing a mean value between both the hold voltages as a central level value.

Claims3

Dependent claims

A circuit for detecting and correcting a central level of an FSK demodulation signal, comprising:

a first holding circuit which holds a first sample signal of a base band signal demodulated of an FSK signal by a first sampler;
a second holding circuit which holds a second sample signal of the base band signal by a second sampler;
shift value calculating means for taking a difference between outputs from the first and second holding circuits to calculate a shift width value;
converting means for analog-digital-analog converting the shift width value;
adding means for adding an analog-converted signal of the converting means to the base band signal;
subtracting means for subtracting the analog-converted signal from the base band signal;
a third sampler which holds a third sample signal of the output of the adding means at the first holding circuit;
a fourth sampler which holds a fourth sample signal at the second holding circuit;
mean value calculating means for taking a mean of outputs of the first and second holding circuits to calculate a central level value of an FSK demodulation signal;
determining means for making determination about “1” or “0” of reception information data of the FSK signal utilizing the central level value as a reference value;
and
control means for controlling a holding function of the converting means and operations of the first to fourth samplers according to the determination result of the determination means.

9 more elements

Dependencies are inferred from the claim text.

Circuit for detecting and correcting central level of FSK demodulation signal

Life of this patent

Circuit for detecting and correcting central level of FSK demodulation signal

Life of this patent

Abstract

Claims3