US 2003/0151448 A1 · Negative voltage output charge pump circuit

Abstract

In a negative voltage output charge pump circuit, first a capacitor C1 is charged with a positive voltage Vin relative to a reference voltage, and then the high-potential terminal A of the capacitor C1 is made to conduct to the reference voltage and simultaneously the low-potential terminal B of the capacitor C1 is made to conduct to an output terminal OUT so that the voltage with which the capacitor C1 is charged is output as a negative voltage −Vin. Here, at least one of the switching device DP1 that is kept on while the capacitor C1 is being charged so as to apply the reference voltage to the point B and the switching device DP2 that is kept on while the negative voltage is being output so as to make the point B conduct to the output terminal OUT is a depletion-type transistor. This configuration makes it possible to realize a negative voltage output charge pump circuit that is free from malfunctioning caused by a parasitic device, that operates with low loss, and that can be produced at low costs.

Claims8

Dependent claims

A negative voltage output charge pump circuit comprising:

a capacitor that, while being charged, receives, at one end thereof, a reference voltage and receives, at another end thereof, a positive voltage relative to the reference voltage and that, while being discharged, has said another end thereof conducting to the reference voltage and has said one end thereof conducting to an output terminal;
a first switching device that is kept on while the capacitor is being charged so as to apply the reference voltage to said one end of the capacitor;
and
a second switching device that is kept on while the capacitor is being discharged so as to make said one end of the capacitor conduct to the output terminal,
wherein at least one of the first and second switching devices is of a depletion type.

2 more elements

A negative voltage output charge pump circuit comprising:

first and second capacitors that are individually charged with and discharged of electric charge;
a reference terminal to which a reference voltage is applied;
an input terminal to which a positive voltage relative to the reference voltage is applied;
an output terminal from which a negative voltage relative to the reference voltage is output;
a first switching device connected between the input terminal and one end of the first capacitor;
a second switching device connected between the reference terminal and another end of the first capacitor;
a third switching device connected between said another end of the first capacitor and a point between one end of the second capacitor and the output terminal;
and
a fourth switching device connected between said one end of the first capacitor and a point between another end of the second capacitor and the reference terminal,
wherein the first switching device is an enhancement-type PMOS transistor, at least one of the second and third switching devices is a depletion-type PMOS transistor, and the fourth switching device is an enhancement-type NMOS transistor,
the first capacitor being charged with the positive voltage when the first and second switching devices are on and the third and fourth switching devices are off,
the voltage with which the first capacitor is charged being output as the negative voltage from the output terminal when the first and second switching devices are off and the third and fourth switching devices are on.

9 more elements

Dependencies are inferred from the claim text.

Negative voltage output charge pump circuit

Life of this patent

Negative voltage output charge pump circuit

Life of this patent

Abstract

Claims8