US 2003/0151441 A1 · Interleaved clock signal generator having serial delay and ring counter architecture

Abstract

The interleaved clock generator generates N interleaved clock signals in response to an input clock signal. The interleaved clock generator comprises an interleaved clock generator of a first type for receiving the input clock signal and for generating M interleaved intermediate clock signals in response to the input clock signal. The interleaved clock generator of the first type includes either a multi-stage serial-delay circuit or a ring counter circuit. The interleaved clock generator additionally comprises M interleaved clock generators of a second type, each of which is each for receiving a respective one of the intermediate clock signals from the clock generator of the first type and for generating N/M of the N interleaved clock signals in response to the respective one of the intermediate clock signals. Each of the interleaved clock generators of the second type includes either a ring counter circuit or a multi-stage serial-delay circuit: a ring counter when the interleaved clock generator of the first type includes a multi-stage serial-delay circuit; a multi-stage serial-delay circuit when the interleaved clock generator of the first type includes a ring counter circuit.

Claims20

Dependent claims

An interleaved clock generator for generating N interleaved clock signals in response to an input clock signal, the interleaved clock generator comprising:

interleaved clock generator means of a first type for receiving the input clock signal and for generating in response thereto M interleaved intermediate clock signals, the interleaved clock generator means of the first type including one of (a) a multi-stage serial-delay circuit and (b) a ring counter circuit;
and
M interleaved clock generator means of a second type, each for receiving a respective one of the intermediate clock signals from the clock generator means of the first type and for generating in response thereto N/M of the N interleaved clock signals, each of the interleaved clock signal generator means of the second type including the other of (a) the multi-stage serial-delay circuit and (b) the ring counter circuit.

An interleaved clock generator for generating N interleaved clock signals in response to an input clock signal, the interleaved clock generator comprising:

an interleaved clock generator of a first type, including a clock input connected to receive the input clock signal, M intermediate clock outputs, and one of (a) a multi-stage serial-delay circuit and (b) a ring counter circuit, the interleaved clock generator of the first type operating in response to the input clock signal to output a respective intermediate clock signal at each of the intermediate clock outputs;
and
M interleaved clock generators of a second type, each including an intermediate clock input connected to a different one of the M intermediate clock outputs of the interleaved clock signal generator of the first type, N/M clock outputs and the other of (a) the multi-stage serial-delay circuit and (b) the ring counter circuit, each of the interleaved clock generators of the second type operating in response to the intermediate clock signal to output a respective one of N/M of the interleaved clock signals at each of the clock outputs.

Dependencies are inferred from the claim text.

Interleaved clock signal generator having serial delay and ring counter architecture

Life of this patent

Interleaved clock signal generator having serial delay and ring counter architecture

Life of this patent

Abstract

Claims20