US 2003/0151440 A1 · Digital clock generator

Abstract

The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital data input (3) for applying a settable digital increment value, of an adder (6) for adding the increment value with the feedback digital cumulative value of the adder, of an output register (13) for outputting the highest order data bit of the digital cumulative value as an output clock signal of the clock generator (1) over an output clock line, and of a digital phase deviation calculating unit (30) for calculating the phase deviation of the output clock signal according to the remaining low-order data bits of the digital cumulative value and of the digital increment value, whereby the phase deviation is output as a digital phase deviation value to a digital data output (29).

Claims13

Dependent claims

Digital clock generator including

a system clock input (2) to apply a high-frequency system clock signal;
a digital data input (3) to apply an adjustable digital incremental value;
an adder (6) to add the incremental value to the feedback digital summed value of the adder;
an output register (13) to output the most-significant data bit of the digital summed value as the output clock signal of the clock generator (1) through an output clock line (33);
and including
a digital phase deviation calculation unit (30) to calculate the phase deviation of the output clock signal as a function of the low-order data bits of the digital summed value and of the digital incremental value, wherein the phase deviation is output as a digital phase deviation value to a digital data output (29).

3 more elements

Dependencies are inferred from the claim text.

Digital clock generator

Life of this patent

Digital clock generator

Life of this patent

Abstract

Claims13