Semiconductor integrated circuit device and delay-locked loop device

A semiconductor integrated circuit device, comprising:

• an input buffer for receiving a clock signal applied thereto;
• a first delay-locked loop circuit including:
• a first delay line, receiving the clock signal output from said input buffer, for outputting a signal, obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a first phase detector, receiving the clock signal output from said input buffer and the signal output from said second delay line, for detecting a phase difference between the two signals;
• a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines;
• and
• a first aligner, receiving the signal output from said first delay line as a latch timing signal, for latching the tap selection signal output from said first counter and supplying the latched signal to said first and second delay lines;
• a second delay-locked loop circuit including:
• a third delay line, receiving the clock signal output from said first input buffer, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a first multiplexer, receiving two output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals;
• a dummy second multiplexer, receiving the output signal of said first multiplexer;
• a dummy first buffer, receiving an output signal of said second multiplexer and having a delay time identical with that of an output buffer;
• a dummy second buffer, receiving an output signal of said dummy first buffer and having a delay time identical with that of said input buffer;
• a second phase detector, receiving the clock signal output from said input buffer and a signal output from said dummy second buffer, for detecting a phase difference between the two signals;
• a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and delay lines;
• and
• a second aligner, receiving the output signal of said first multiplexer as a latch timing signal, for latching the tap selection signal that is output from said second counter and supplying this signal to said third and fourth delay lines;
• and
• a third multiplexer, receiving the signal output from said first multiplexer as a data-output clock, for selecting and outputting one item of data among a plurality of items of data applied thereto;
• said second multiplexer having a delay time identical with that of said third multiplexer;
• said output buffer, receiving a signal output from said third multiplexer, outputting the signal as output data from an output terminal.

A semiconductor integrated circuit device, comprising:

• an input buffer for receiving a clock signal applied thereto;
• a delay-locked loop circuit including:
• a delay line, receiving the clock signal output from said input buffer, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a first multiplexer, receiving the output signal of said delay line;
• a dummy first buffer, receiving an output signal of said first multiplexer and having a delay time identical with that of an output buffer;
• a dummy second buffer, receiving an output signal of said first buffer and having a delay time identical with that of said input buffer;
• a phase detector, receiving the clock signal output from said input buffer and an output signal of said dummy second buffer, for detecting a phase difference between the two signals;
• a counter, receiving an output signal from said phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said phase detector and for outputting a tap selection signal that changes over the output tap of said delay line;
• and
• an aligner, receiving the output signal of said delay line as a latch timing signal, for latching the tap selection signal output from said counter and supplying the latched signal to said delay line;
• and
• a second multiplexer, receiving the signal output from said delay line as a data-output clock, for selecting and outputting one item of data among a plurality of items of data applied thereto;
• said first multiplexer having a delay time identical with that of said second multiplexer;
• said output buffer, receiving a signal output from said second multiplexer, outputting the signal as output data from an output terminal.

A delay-locked loop device comprising:

• a first delay-locked loop for adjusting delay times of serially connected first and second delay lines in such a manner that a signal obtained by delaying an input signal by the first and second delay lines is in phase with the input signal, thereby outputting, from the first delay line, a signal that is the result of delaying the input signal by one half cycle of the input signal, said first delay-locked loop including:
• a frequency dividing circuit for performing frequency division of the input signal, an output signal from said frequency dividing circuit being delayed by said first and second delay lines;
• and
• first delay adjustment means for outputting a control signal for adjusting the delay times of said first and second delay lines in such a manner that the output signal of said frequency dividing circuit and an output signal of said second delay line are in phase;
• and
• a second delay-locked loop for generating a data-output clock signal based upon the input signal and supplying the data-output clock to a multiplexer that selectively outputs multiple items of data, said second delay-locked loop including:
• a third delay line, receiving the output signal of said frequency dividing circuit, for outputting a first signal by delaying this output signal;
• a fourth delay line, receiving an output signal of said first delay-locked loop device, for outputting a second signal by delaying this output signal;
• a circuit, receiving the first and second signals from said third and fourth delay lines, respectively, for outputting, as the data-output clock, a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the first and second signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones of the first and second signals;
• and
• second delay adjusting means for outputting a control signal for adjusting delay times of said third and fourth delay lines in such a manner that a signal obtained by delaying the data-output clock by at least a delay time of said multiplexer is in phase with the input signal.

A delay-locked loop device comprising a first delay-locked loop and a second delay-locked loop;

• said first delay-locked loop including:
• a first delay line, receiving a clock signal obtained as a result of dividing frequency of a clock signal, which is output from an input buffer having the clock signal applied thereto, by a frequency divider, for outputting a signal obtained by delaying the frequency-divided clock signal, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a first phase detector, receiving the frequency-divided clock signal and a signal output from said second delay line, for detecting a phase difference between the two signals;
• and
• a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines;
• and
• said second delay-locked loop including:
• a third delay line, receiving the frequency-divided clock signal output from said frequency dividing circuit, for outputting a signal obtained by delaying the frequency-divided clock signal, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a first multiplexer, receiving output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals;
• delay means for delaying the signal output from said first multiplexer a predetermined length of time;
• a second phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals;
• and
• a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and delay lines.

A delay-locked loop device comprising a first delay-locked loop and a second delay-locked loop;

• said first delay-locked loop including:
• a first delay line, receiving a clock signal output from an input buffer having the clock signal applied thereto, for outputting a signal obtained by delaying the clock signal from the input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a second delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a first phase detector, receiving the output clock signal of the input buffer and a signal output from said second delay line, for detecting a phase difference between the two signals;
• a first counter, receiving an output signal from said first phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said first phase detector and for outputting a tap selection signal that changes over the output taps of said first and second delay lines;
• and
• a first aligner, receiving the output signal of said first delay line as a latch timing signal, for latching the tap selection signal output from said first counter, and supplying the latched signal to said first and second delay lines;
• and
• said second delay-locked loop including:
• a third delay line, receiving the clock signal output from the input buffer, for outputting a signal obtained by delaying the clock signal from the input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a fourth delay line, receiving an output signal of said first delay line, for outputting a signal obtained by delaying the output signal of said first delay line, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• a first multiplexer, receiving output signals of said third and fourth delay lines, for outputting a signal in which timings of rising and falling edges of a pulse are decided by rising edges of respective ones of the two output signals, and in which timings of rising and falling edges of a succeeding pulse are decided by falling edges of respective ones the two output signals;
• delay means for delaying the signal output from said first multiplexer a predetermined length of time;
• a second phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals;
• a second counter, receiving an output signal from said second phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said second phase detector and for outputting a tap selection signal that changes over the output taps of said third and delay lines;
• and
• a second aligner, receiving the output signal of said first multiplexer as a latch timing signal, for latching the tap selection signal output from said second counter, and supplying this signal to said third and fourth delay lines.

A delay-locked loop device comprising:

• a delay line, receiving a clock signal that is output from an input buffer having the clock signal applied thereto, for outputting a signal obtained by delaying the clock signal from said input buffer, from an output tap selected from among a plurality of output taps having delay times that differ from one another;
• delay means for delaying the signal output from said delay line a predetermined length of time;
• a phase detector, receiving the clock signal output from said input buffer and an output signal of said delay means, for detecting a phase difference between the two signals;
• and
• a counter, receiving an output signal from said phase detector, for changing a count value in accordance with a phase lead/lag relationship represented by the output of said phase detector and for outputting a tap selection signal that changes over the output tap of said delay line;
• and
• an aligner, receiving the signal output from said delay line as a latch timing signal, for latching the tap selection signal that is output from said first counter and supplying this signal to said delay line.