5 Volt tolerant input/output buffer
OwnerPaul H. OuYanginventor
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Abstract
A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its input/output (I/O) node, while operating with a 3 volt power supply and is resistant to CMOS latchup. The 5 volt compatibility is achieved by inserting an additional p-channel transistor in series with the existing p-channel transistor and circuitry to control the additional p-channel transistor. The control circuit is comprised of 2 transistors. The CMOS latchup resistance is provided by a N-well bias generator that changes the N-well bias to be equal to the higher of the 2 voltages, VDD or the voltage present at the I/O pad. The N-well bias generator is comprised of 3 transistors.
Claims20
A tristate buffer comprising:
- a power supply providing a supply voltage;
- an input buffer coupled to receive the supply voltage;
- an output buffer coupled to receive the supply voltage and to an input-output node;
- a control circuit coupled with the input buffer and the output buffer, the control circuit being coupled to receive the supply voltage;
- and
- a bias circuit coupled with the input buffer, the output buffer, and the control circuit,
- wherein an output voltage at the input-output node comprises a voltage approximately equal to either the supply voltage or an external voltage.
A tristate buffer comprising:
- a power supply providing a supply voltage;
- an input buffer coupled to receive the supply voltage;
- an output buffer coupled to receive the supply voltage, the output buffer comprising a first transistor and a second transistor coupled between the supply voltage and an input-ouput node;
- a control circuit coupled with the input buffer and the output buffer, the control circuit being coupled to receive the supply voltage;
- and
- a bias circuit the input buffer and the output buffer, and the control circuit.
An output buffer of tristate buffer comprising:
- a first transistor having a drain coupled to a supply voltage, a gate coupled to a control circuit, and a source;
- a second transistor having a drain coupled to the source of the first transistor, a gate coupled to the control circuit, and a source coupled to an input-output node of the tristate buffer;
- and
- a third transistor having a drain coupled to the source of the second transistor, a gate coupled to the control circuit and a source.
Dependencies are inferred from the claim text.