Vertical electronic circuit package and method of fabrication therefor

A method for fabricating an electrical assembly, the method comprising:

• fabricating a first multiple layer structure, which includes multiple first patterned conductive layers oriented in parallel with a first plane, wherein a top surface and a bottom surface of the first multiple layer structure are in parallel with a second plane that is substantially perpendicular to the first plane;
• forming a first set of conductive pads on the top surface in direct contact with the first patterned conductive layers;
• and
• forming a set of connectors on the bottom surface in direct contact with the first patterned conductive layers.

A method for fabricating an integrated circuit package, the method comprising:

• fabricating a first package structure, which includes multiple first patterned conductive layers oriented in parallel with a first plane and which include multiple conductive traces that electrically connect a top surface and a bottom surface of the first package structure, wherein the top surface and the bottom surface are in parallel with a second plane that is substantially perpendicular to the first plane;
• forming a first set of conductive pads on the top surface in direct contact with the multiple conductive traces;
• and
• forming a set of connectors on the bottom surface in direct contact with the multiple conductive traces.