Semiconductor packaging device and manufacture thereof

A semiconductor packaging device comprising:

• a carrier having at least a slot via said carrier;
• at least a chip having a back surface and an active surface, wherein said chip is affixed to said slot to expose said active surface, and said active surface has a plurality of first bonding pads;
• a first insulating layer on said active surface and said carrier, said first insulating layer comprising a plurality of first plating through holes connected to first bonding pads and via said first insulating layer;
• a multi-layer structure on said first insulating layer, said multi-layer structure comprising a plurality of conductive layout lines, a plurality of second plating through holes therein, and a second insulating layer and a plurality of exposed ball pads thereon, wherein said first plating through holes are electrically connected with said conductive layout lines, said second plating through holes, and said exposed ball pads;
• and
• a plurality of solder balls affixed to said ball pads.

A semiconductor packaging device comprising:

• a carrier having a circuit layout therein, a first surface with a plurality of ball pads, and a second surface with a cavity thereon and a plurality of first bonding pads;
• at least a chip having a back surface and an active surface with a plurality of second bonding pads thereon, wherein said chip is affixed to said cavity to expose said active surface;
• a first insulating layer on said active surface and said carrier, said first insulating layer comprising a plurality of first plating through holes connected to first bonding pads, said second bonding pads, and said first plating through holes via said first insulating layer;
• a multi-layer structure on said first insulating layer, said multi-layer structure comprising a plurality of conductive layout lines, a plurality of second plating through holes therein, wherein said conductive layout lines, said second plating through holes are connected to said first plating through holes and electrically connected to said ball pads;
• and
• a plurality of solder balls affixed to said ball pads.

A semiconductor packaging device comprising:

• a carrier having a circuit layout therein, a first surface with a plurality of ball pads, and a second surface with a slot via said carrier and a plurality of first bonding pads;
• at least a chip having a back surface and an active surface with a plurality of second bonding pads thereon, wherein said chip is affixed to said slot to expose said active surface on said second surface and expose said back surface on said first surface;
• a first insulating layer on said active surface and said carrier, said first insulating layer comprising a plurality of first plating through holes connected to first bonding pads, said second bonding pads, and said first plating through holes via said first insulating layer;
• a multi-layer structure on said first insulating layer, said multi-layer structure comprising a plurality of conductive layout lines, a plurality of second plating through holes therein, wherein said conductive layout lines, said second plating through holes are connected to said first plating through holes and electrically connected to said ball pads;
• and
• a plurality of solder balls affixed to said ball pads.