US 2003/0151137 A1Published application

Semiconductor device

AssigneeSanyo Electric Co., Ltd.

InventorsTetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura

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Abstract

A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.

Claims17

Dependent claims

A wiring board for mounting a surface mounted element thereon, comprising:

an insulating substrate;
a first terminal disposed on the substrate;
a first lead disposed on the substrate and extending from the first terminal;
an insulating layer disposed on the first terminal, the first lead and the substrate;
a second terminal disposed on the insulating layer;
a second lead disposed on the insulating layer and extending from the second terminal;
a third terminal disposed on the insulating layer;
a third lead disposed on the insulating layer and extending from the third terminal, a portion of the third lead being configured to have the surface mounted element mounted thereon;
and
a fourth lead disposed on the insulating layer, the first terminal and the fourth lead being disposed opposite to each other with respect to the second lead,
wherein the first and second terminals are disposed on a same side of the wiring board with respect to the mounting portion of the third lead, and
the first lead runs underneath the mounting portion of the third lead and is connected to the fourth lead.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/310,139Filed 5 Dec 2002
Priority: JP 2001-3723136 Dec 2001
Published: 14 Aug 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 70/65
Characterised by their interconnections: shapes or dispositions of interconnections
H10D 84/01
Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers:…
H10W 42/20
Arrangements for protection of devices: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
H10W 44/20
Electrical arrangements for controlling or matching impedance: at high-frequency [HF] or radio frequency [RF]