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AssigneeHitachi, Ltd.
InventorsHiroshi Toyoshima, Atsuhiro Hayashi, Takemi Negishi, Takashi Uehara
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A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.
A semiconductor integrated circuit device comprising:
A semiconductor integrated circuit device comprising:
Dependencies are inferred from the claim text.