Semiconductor memory device
AssigneeNEC Electronics Corporation
InventorKohichi Kuroki
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Abstract
A semiconductor memory device of the present invention having sense amplifier transistors connected to complementary bit lines of a memory cell array and sense amplifier driver transistors driving the sense amplifier transistors, wherein the sense amplifier transistors and the sense amplifier driver transistors have gate electrodes dividing a common diffusion layer region formed on the surface of a semiconductor substrate into two, respectively, the gate electrodes being arranged on the boundary of the diffusion layer region.
Claims5
A semiconductor memory device having sense amplifier transistors connected to complementary bit lines of a memory cell array and sense amplifier driver transistors driving said sense amplifier transistors, wherein
- said sense amplifier transistors and said sense amplifier driver transistors have gate electrodes dividing a common diffusion layer region formed on the surface of a semiconductor substrate into two, respectively, the gate electrodes being arranged on the boundary of said diffusion layer region.
Dependencies are inferred from the claim text.